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Recent content by chaitubek

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    Question About RTL Compiler

    rtl compiler report Hi, I have one doubt?? How to set max_area constraint in RTL compiler? there is no dc::set_max_area in rc any RTL Compiler related command for setting the max area constraint? Thanks in advance Chaitanya.
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    Setting QRC in to Virtuoso Layout editor

    qrc parasitics extraction manual Hi, I am using QRC (EXT8.1 version) for extraction. I have set the QRC_HOME varible properly. When I open Layout editor, I am not seeing QRC tab in the GUI. I want to see QRC in the Layout editor. Is any seetings I need to do? Please help me Thanks in...
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    Reg excempting timing arc check

    Hi Polu, As you told, the most restrictive edge between two clocks is 0.1 later 0.2 and 0.3 You want to skip 0.1 ns, remaining checkes u need to be done. If we r using mcp, it will chekc for more time.( not 0.2 and 0.3). Here in this case, if we check for 0.2 ns, no need to check for 0.3ns...
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    checki ng of verilog netlist before Place & Route

    1) No inputs should be floated. 2) There should not any assign statements. 3) All floating input connected to tie cells. 4) Adding Spare cells ( It depends on methodology, some guys will put in the P&R) 5) proper naming rules for the netlist etc.... Thanks, Chaitanya.
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    Reg excempting timing arc check

    Hi Polu, I understood ur question like this, say CLK1 is higher frequency than the CLK2. CLK1 is triggering the lauching flop, and CLK2 is triggering the capture flop. By default if u dont tell any relation for the two clocks in PT, It will calculate the LCM of two clocks, i.e, it will check...
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    Why Hold Violation is Fixed in Min Corner?

    min delay violation Fixing the hold violations in the mincorner does not give the guarantee that it will fix the hold violations in the max corner also automatically, because the delays at different corners are not linear. we need to fix the hold violations in min and max corner. Thanks...
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    How important is the check_design command for synthesis in DC?

    check_design, design compiler Hi, Make sure that you read all the modules of your verilog netlist. Thanks Chaitanya
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    Effects of increased sampling rate for FIR Filter in Matlab

    Re: FIR Filter in Matlab can u send me ur matlab code. my email chaitubek@yahoo.co.in thank u,.. plz.. its urgent

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