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Recent content by chaitu2k

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    McClellan, Schafer and Yoder, DSP FIRST

    Hi, Could anyone upload the following book "McClellan, Schafer and Yoder, DSP FIRST: A Multimedia Approach, 2nd edition. "... or point me to a link where i can download it for free... Cheers
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    Xilinx FPGA Area Utilization

    area utilization xilinx Hi, what Aastik said is correct....and yes PnR tools does spread the logic a bit for timing but in your case the spreading does not seem to be more as LUT utilization is 95%....u could still add a liitle more logic if it does not affect your performance...then pnr will...
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    C/Verilog code for CRC calculation for polynomials

    Re: CRC calculation hi go to this website https://www.easics.com/webtools/crctool it is a crc tool which generates VHDL or VERILOG code for any given CRC polynomial and any databus width...its FREE....and its the best enjoy!!
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    how fpgas are used in mobile commu applications

    xilinx coolrunner II cplds are used in mobile phones...
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    Please help me with implementing a cam in a fpga

    Re: cam in fpga U cld do it using Dual port Block RAMS available in Xilinx FPGAS. it would take abt 6 such Dual port BRAMS to implement your CAM abt 200 - 300 slices and 3-4 clocks for the output result ..depending on your coding skills...refer to xilinx document on implementing CAM...XAPP260....
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    ASIC Code to FPGA Code Conversion

    try to identfy all multicycle and false paths in ur design....relax the constraints for these.....if possible also try using the xplorer perl script from xilinx....
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    How to make use of .edn files in Xilinx project?

    Re: Net List files hi yes edn files are generated by xoregen....if u want to simulate then coregen also generates .vhd and .v files which r present in ur working directory... u can include these files in ur modelsim project and simulate if xilinx coregen libraries are complied in...
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    Xilinx warning: HDLParsers:3498 - No primary, secondary unit in the file

    hdlparsers:3498 yes...i think osbourne is correct...since i sometimes used to get this error in 6.3i....but it gives a black box generating warning in 7.1i.....
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    MICROBLAZE : OPB-IP interface

    hi I need to connect at 72-bit wide block ram on a 32-bit wide data bus of microblaze...i think to achieve this in need to interface my bram with opb-ip i.e treat my Bram as an ip....but i still dont know how...as its the first time i'm going to implement microblaze...any ideas or docs are...
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    starting point on PCB design

    learn pcb design hi all i'm interested in learning PCB design...but its new 2 me...and i need a starting point...could some one give me reading material...or tips cheers
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    mostly used verification language in industries?

    could anyone tell whts best with modelsim....is tcl/tk the most supported by modelsim or whts better thnks
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    PYTHON for VERIFICATION

    ncsim scriptsim hi all i have heard that python is good for RTL verification ....I know it is easy to learn...but before i go ahead can some one tell me whether it can be interfaced with modelsim and what is the verification flow to be followed or anyone have documents abt this pls....also it...
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    Resources for beginners in FPGA

    Re: need help about FPGA here is a gud PDF... Programmable Logic Design Quick Start Hand Book --Second edition By Karen Parnell & Nick Mehta -- Xilinx I also found an article on intermediate fpga in this forum which is gud.....i suggest tht u go through the article uploaded by me first and...
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    VHDL to Verilog Problem !

    can anyone foward or suggest good verilog to vhdl conversion and vice versa software.... also are there any drawbacks in using the conversion softwares
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    What's the use of "&" operator in VHDL?

    bitwise or in vhdl & - concatination and - bitwise and operation any VHDL book will tell u this
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