Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi,
I have 330 internal core chains to each edt_channel and there are 7 edt_channels in my EDT logic. when I was performing simulation in synopsys vcs, the log file is reporting that a flop is producing x instead of 1, in edt_channel 2.
How to fix it.
Regards,
chaitanya.
Hi,
I was asked to perform pattern retargetting for a block which is present in the main block that consists of four other blocks.
why I should make the block as blackbox instead of graybox during pattern retargetting?
Hi,
I was performing simulation(scan_serial) in synopsys vcs for one block named rx_pd after performing pattern retargetting.
I got an error saying that Mismatch occurred
Signal name: SEL_VAUX_B
timestamp : 31290ns
instance : topmodule/submodule/core/edt_rx_pd_channel2
Simulated : x...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
