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Recent content by chaitanya163

  1. C

    Generating a desired synthesizable binary pulse train on FPGA using VHDL

    Hi Thank you everyone for responding and being patient with me. Simulated and its working. Will create TB now. Is there any good book that you can suggest for digital circuits(possibly available online) which I can read to enhance my understanding and to make my concepts more clear. Thank...
  2. C

    Generating a desired synthesizable binary pulse train on FPGA using VHDL

    Hi Ads-ee sorry to disappoint you but yes I am starting from the basics. Just a last question that can I specify some 16 bit pulse train like "1011001011001010" in the Xilinx ISE software and with the on board clock that I have can I have this pulse train output serially on the one pin of the...
  3. C

    Generating a desired synthesizable binary pulse train on FPGA using VHDL

    Hi Tricky I am unfortunately not aware of any method of doing it with the clock. It will be very kind of you to let me know how it can be done. Thanks Regards
  4. C

    Generating a desired synthesizable binary pulse train on FPGA using VHDL

    Hi thank you for your suggestions. So I have 16 digital IO pins on my FPGA kit , so if I wish to generate for example 10 bit pulse train then will I have to use the 10 bit shift register for the input signal ? Also do I have to use 10 pins for the input signal and 10 pins for the output...
  5. C

    Generating a desired synthesizable binary pulse train on FPGA using VHDL

    Hello everyone I am new to VHDL programming and FPGA. I have a virtex - 4 FPGA and I wish to generate a binary pulse train of 16 pulses from FPGA using VHDL programming. My desired pulse train will be like "1011100111000110"(min pulse width = 30 ns). I have a clock of 100 MHz and I am able to...
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