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Recent content by cfft

  1. C

    analysis the clk's phase noise on ADC's block performance?

    Can anyone help me to analysis the clk's phase noise on adc's block performance in detail? Or is there any analysis article on it? Much thanks.
  2. C

    does anyone has good implementation of complex filter?

    Does anyone has good implementation of complex filter in FPGA? Would you so kind to share the implementation method with me? Thank you.
  3. C

    The Effect of Quadrature Modulator and Demodulator Errors..

    IEEE paper required: The Effect of Quadrature Modulator and Demodulator Errors on Adaptive Predistortors for amplifer linearizaion Author:James K.Cavers,IEEE 0018-9545/97.pp.456-466. The paper is about how to cancel the dc offset and IQ imblance produced by the AQM process. Does anyone help...
  4. C

    Looking for pictures of US patent no. 4.635.070

    Re: about US patent ,635,070 But I can't find the figure in the patent full text. Where can I find them?Would you please help me how to do it? Much thanks.
  5. C

    about soft radio - any materials?

    Re: about soft radio Maybe there are some other sampling technology. Such as pipeline sampling. If the sampling clk is good enough,then pipeline samping is possible and realistic.
  6. C

    IEEE papers required:Henry Samueli,"On the design of Op

    Does anyone help me get the following IEEE papers: Henry Samueli,"On the design of Optimal Equiripple FIR Digital Filters for Data transmission Applications",IEEE Transactions on Cirsuits and Systems,Vol.35,No.12,December 1988. Much thanks!
  7. C

    How to avoid using clk buffer ?

    Re: How to avoid clk buffer If you use synplifypro,you can find it from its help menu. I forget it now.It may be add the attribute ,'syn_no_clkbuf',to the input clk. You can try it or find from the help menu through finding syn_no_clkbuf. Good luck!
  8. C

    Help me design an 8x upsampling filter

    upsampling tiefpassfilter FYI.
  9. C

    Will Altera Cyclone PLL support such clocks?

    Re: Altera Cyclone PLL I have heard that the PLL in altera fpga devices is not function well. If you want to use the fration multiple,the performance is not good. How about the abate ratio of the PLL in altera device?anyone can confirm it? Thanks!
  10. C

    how to force the syntheziser to keep a signal

    If you use synplifypro,it's very easy to do it from the help of synplify.
  11. C

    about sparten3 and 90nm technics

    Xilinx has announced the sparten3 series fpga with surprising price. but now Altera say 90nm technics is for 2005 only.Then can xilinx supply sparten3 fpga 2004 quantified? Anyone can confirm it to me?Thanks!
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