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Sorry, I didn't get what you were saying. I thought the two nmos will operate first at linear region, and then as the drain voltage became large enough, they will operate at saturation region. So the Id vs Vd plot is the same as the Id vs Vds plot for single nmos at certain Vgs.
Please let me...
I answered that as node A ramp from 0 to 2V, the nmos is on, and Vgd=Vth, the voltage on node B should be Vth lower than the gate voltage, so node B will be 2V. (However, I always confuse that why Vgd will stay equal to Vth, I know that Vgd<Vth for saturation, and Vdg>Vth for linear region). As...
I was asked that two nmos in a cascode topology, the bottom nmos source connected to ground. The two nmos gates were biasing by Vb1 and Vb2, where Vb2>Vb1>Vth.
Question: As we sweep the drain node of the top nmos Vd from 0V to some very large voltage, how the drain current change with Vd?
I was asked that there is a nmos with Vth=1V, gate voltage Vg=3V. One end of the nmos node B (source/drain) is connected with a small capacitor (almost instantly charged), and the other end node A (source/drain) is swept from 0V to 3V.
Question: How is the voltage at node B changed as node A...
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