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Hello Everyone,
I am just starting with a new board, a landboard with a nxp LPC1768 programmed with an external ulink2 with keil4.
I do not understand why when i go in debug mode the starting point of my PC is 0x1fff0080
I use the startup code given by keil 4 lite. This address is not random...
The first tips:in order to same power you can use the clock gaiting tecquique by enabling it when you elaborate your design.
In general, power isn't optimized at syntesis level but at design level by using some usefull advice.
Then you can use the syntesis process to further optimize your...
Hi to all,
how can I loop through each rgister from r0 to r7?
I have some data in the registers r0:r7 and i want to compare them with a constant; i need to put 8 line of sub and cmp or is there any solution with branches in order make the solution more clever like a "branch for registers".
I...
Re: modelsim simulation after syntesis
Thank you for your reply.
In my library folder i have 1 file .lib and 1 .db.
I tried to import them in modelsim but it doesn't recognize as library. Where can i find that verilog file to link in modelsim? are any method to import .lib file into modelsim...
I manage to solve my problem with the method you have proposed! :-D
actually it was so simple but i hadn't even thought this solution, maybe because i was so involved in the vhdl that i was focused in many different code configuration! :bang:
Thank you so much!
modelsim simulation after syntesis
Hi to all,
I wonder if it is possible to simulate a synthesised netlist by design compiler in modelsim.
I'm finding that after the synthesis of design vision the output is a file with some component of my library instanciated, for example this:
component...
Hi to all,
I want to build a simple FSM in vhdl where the output is the same of the state encoding of the FSM.
I want this behaviour because I want to change the state encoding at every syntesis (with the command set_fsm_encoding in DC) and make some consideration.
For example, given a simple...
Hi to everybody,
I’m a little bit confused about how to simulate an entity on modelsim in tcl.
I tried to find some guide by googling but i found lots of command that are hard to be understood.
My problem is that i would like to simulate a vhdl file, whith an entity called ‘addertb’ with a...
Thank you for your replies.
It's straightforward for a counter, and i can not refear to any datasheet because i'm implementing a fsm in vhdl so i'd like to know the differences between the two signals in order to implement the correct one. For sure reset is mandatory, but what about enable...
have you connected the pickit 2 properly?
have a look at this photo:
http://www.eobdtool.com/editor/attached/20170419/20170419170254_94725.png
If yes, verify the connection between the programmer and the pic by looking the 16F887 datasheet and by checking if every pin involved in the photo is...
Hello everybody,
I'm a little bit confused about the difference of reset and enable in digital IC...
for a design point of view, the enable signal helps to prevent glitches at the output port, so by enabling the circuit only when the data inputs are ready the output hasn't got any of it.
the...
Re: Modelsim - Different istance of the same unit
thanks for your reply. It is not a hierarchical design becouse the registers haven't got any correlation between each other.
What i'm trying to do is to simulate different block in simulink using HDL verifier. My purpose is to build an...
Re: Modelsim - Different istance of the same unit
so your suggestion is to rename the external file by mean of doing multiple copies of the same design unit and import them to modelsim. is this your idea or i'm misunderstanding?
i wanted to do it inside modelsim becouse i'd like to export the...
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