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Recent content by carbon_79

  1. C

    Case statement in Verilog

    It seems the definition a bit error . If it's a 5 bit addr, it cannot represent 5'h20 as it can only be 0 or 1 . i guess the addr should be 5'b01000 //case 1 , 5'h08 5'b01001 //case 2 , 5'h09 5'b01010 //case 3 , 5'h0A 5'b10000 //case 4 , 5'h10 or 6 bit addr 6'b010000 //case 1 , 6'h10...

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