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Hi all, I have a problem. I have coded a vhdl module with some generics to parameterized the design based on width bus. In the design I have a counter and I need to stop the counter when it has achieved the half value. So, I've declared a constant but Active HDL gives me an error. I declared...
Hi all,
I'm looking for a way to identify my generated bitstream design from the file. I've found **broken link removed** paper. They talk about a comment string in the bitstream. Does anyone know a way to add this comment in the bitstream ?
Hi all,
I've a problem with the installation of the TSMC 65n LVS file for Assura. I've downoladed the PDK from europractice, but I don't know where I can find the file for LVS. Can anyone give me some infos about the name of the file that I need ? Thanks in advice.
Cheers
Hi all, I have a problem with the simulation of a simple buffer. When I start the simulation from ADE-L, I get this error from Spectre :
Simulating `input.scs' on sirio.dftgroup.uniroma2.it at 2:58:08 PM, Mon Jun 11, 2012 (process id: 18499).
Command line...
I've resolved but I don't know what I've done to make it work. I'm following a tutorial that I've found in the PDK folder. Now I've some problems with the corner simulation in Spectre, but I am confident of being able to solve. Thanks all.
Hi all,
I state that I'm totally newbie about Cadence tools and PDK ( It's the part of the topic of my thesis ) and that my english is bad. So, I must install TSMC 65 nm PDK. I have a problem with the installation of the PDK library. I've unzipped the multi-part archive and now I have a...
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