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Considering the foundry manufacture, we introduce the OCV to timing analysis. But the derates were added to every cell in clock path, even from the clock source to last common point. As we know, one specific cell will only perform one actual delay, so these detates are unnecessary pessimism...
I want to use LEC to compare the Frontend netlist with the PR netlist, need to add some user mapping. add_mapped_points one by one is too slow. I found the command set_analyze_option -mapping_file <file>, but I don't know the file format. Can someone help me? Thanks a lot!
No matter the subckts in your spice or cdl file whatever, or the cells in your gds, the same cell, subckt only exist once, they will be instantiated one or more times to build your top design. Then the tool check each circuit unit only one time.
As you know, foundry use 2 masks successively to make one layer on chip, so each metal will have 'perfect direction', same masks with large space compared with different masks with small space, of course some
forbidden space and width.
For more details, you can check foundry design rules.
I think there isn't matching problem, I have use this command many times for dff(edge-sensitive) with no problems. This is first time I use this command for latch (level-sensitive). Checking the Primetime guide, it says latch/D should be set in '-from' list, but it still doesn't work. I have no...
After set_multicycle_path 2 -setup -from ... -to ... , it will return '1' which means success, but when report_timing of the 2 points, it still check timing in one cycle
Hi all,
Is there any way to check the fundamental grammar of cdl? Such as the match of .subckt and .end, duplicate subckt, wrong subckt pin number and so on. Because the cdl is written by hand, I don't want to find the cdl grammar error till the lvs verification.
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