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Thanks axcdd!
Actually I just changed the control bit I was using from Block 2 output. I was supposed to use the MSB, but with this interchange I was getting the LSB.
Problem solved! At least so far!
Hello all,
I am sorry if this is a recurrent question, but I tried to look for it in the forum and could not find a good way to elaborate my question in order to find something similar.
My problem is the following:
I have a block outputting data to a vector which is 16 bits (15 downto 0).
The...
Thank you very much for all the responses!
I have been looking for FIFOs and one question appeared...Is it possible to have an asynchronous FIFO (as I have 2 clocks) that deals with Packets?
As I saw in FIFO generator datasheet, it should only be possible to transmit packets using synchronous...
Dear All,
I am developing a design that requires one receiving and one transmitting buffer for Packets (probably 1.5kB AND 9kB).
Between these two buffers I will have a communication line (Which needs to be completely transparent using Aurora Protocol. This line is already built).
It will...
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