Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by cactus_studio

  1. C

    What is the difference and relationship of FDC and FAT interface of MPEG signals?

    What is the difference and relationship of FDC and FAT interface of MPEG signals ? Does anyone has hints about these two mpeg interface ? Thank you.
  2. C

    Clock running, NCVer| log problem, oneshot from

    Re: NCVer|log problem. Hi,jelydonut, You are right this is a oneshot circuit.The oneshot pulse is generateing in the RISING EDGE of 'signal' . I simulated it and source code is attached. I simulated it in Nc-verilog, so some changes may be made in modelsim. cac module oneshot...
  3. C

    How asic synthesis and fpga synthesis are different?

    Re: asic and fpga synthesis? How asic synthesis and fpga synthesis are different? <Yes, They are different software, but I think the main idea below them are same. They are all timing driven. In fact, FPGA synthesiser is more simpler than asic ones. I think, this is because FPAG is more...
  4. C

    Which E1 Framer are most popular (+)

    My friends used a Conexant one. But don't ask me why. I am not quite familar with E1 framer. :) cac
  5. C

    digital linkwitz-riley filter

    linkwitz=riley How to design digital linkwitz-riley filter in audio crossover ? Does anyone have related paper or book about this? Thanks. cac
  6. C

    How can I insert parameter in my Verilog core with NC-SIM?

    ncelab generics Maybe you can use 'parameter' or 'defparam' to defind new parameter in your code body instead of using ncelab options. An advantage of this method is you can change your parameter freely indepent of the programm you choosing, say ,NC-sim or modelsim or other. cactus
  7. C

    About MAC table maintenance in SDS9100i

    About MAC table zoovy, I knew your idea about E1 to ethernet rate adaptation . I read SDS9100i datasheet and found it used some rate adaptation methods . Do you think it is REM or WRED? Another qusetion, Why this device keep a MAC address table inside. Do you think it is needed ? In my...
  8. C

    E1&Ethernet Bridge IC

    Unpack Ip ? Hi my_garden: You said, for one E1 to transmit one 10 baseT it is important not only processinng ethernet frames but also processing IP Packets. But I wander how you can accomodate 10 baseT signal only in one E1? Is that possible? Although I know in processing Etherenet frames...
  9. C

    I have gone to raycom website.

    It seems RC7210 is a good chip of Ethenet to 4*E1 bridges. BUt I can't download its datasheet. :( But I still have a questions to my_garden and other people: when I make an ethernet to E1 bridge, do I have to unpack IP packets? My original thoughts is I can only deal with Ethernet frame and...
  10. C

    where to get test bench with VHDL for SDH chip?

    Write or buy it ! YOu can buy the relative product from sy*opsys or C*dence, they both offer good system level simulation tools. But they are expensive.(:< Or you can write it by your own. To do this, yOu must have good knowledge of ITU-T standards . I wrote one in verilog and it worked well...
  11. C

    E1&Ethernet Bridge IC

    e1to ethernet +mt9075 I am interested in this topic very much and read this topic throughly. And I think a E1- Ethernet bridge is only like a device which can transmit Ethernet frames over E1 pipe transparently with the IP and above level protocol nochanged. This is the second case in...

Part and Inventory Search

Top