Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
you didn't tell the input and output swing and the GBW and Cload requirements for the design. you can probably squeeze out that much gain from 2-stage, if it doesnt hit your GBW spec. Avoid three stages if possible. Folded cascode can also be tried..but you need to know the details i mentioned...
what i meant by asking about architecture was whether you are going for cascode structure at any stage (which would have increased the impedance at that node causing more trouble)...anyways, your Cl is 50 pF so your dominant pole is most likely at the third stage output...can you tell me what is...
what is the architecture of each stage ? what's your load capacitance ? where is your dominant pole coming from ..i mean which stage ?and where are the poles located wrt each other ?
opamp design or opamp application
for design some of the good books are
Design of Analog CMOS IC by Behzad Razavi
Analog Integrated Circuit Design by David Johns/Ken MArtin
CMOS Analog Circuit Design: Allen/Holberg
Analysis and Design of Analog Integrated Circuits by Gray/Meyer - mostly BJTs
Re: Class Project: When doing hand-analysis, where do I star
Hi aoshater,
You are generally given a spec for the design with desired gain, GBW, slew rate, max current etc. In your case you have mentined a current budget of 500 uA, are there any more constraints specified.? if not you can...
Re: What's the parameters should be simulated during design
jitter and phase noise in a vco are usually the critical parameters but then it depends on your spec. what is the most stringent constraint.
yes, you can see it in .lis file, and many other dc operating point parameters.
wondering wether the gm of inverter at dc op point will be zero, considering the fact that the current through it will be zero ?
measuring slew rate
run a transient analysis by giving a large voltage step at the input (rail to rail) to take the opamp in non linear mode of operation, measure the slope of the ouput waveform..that'll give you your slew rate.
Can anyone tell me where I can find an e-book of "Compact Low-Voltage And High-Speed CMOS, BiCMOS, And Bipolar Operational Amplifiers" by Klaas-Jan De Langen And Johan H. Huijsing.
thanks.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
