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In the case of Synopsys Design Compiler as your synthesis tool:
You can use "set_dont_use" command to filter out any std-cells you don't want to use during synthesis. For example "set_dont_use MAXLIB/INVX1" will bar synthesis tool from using INVX1 inverter from MAXLIB library.
Knowing how to...
How DC synthesize your sequential logic heavily depends on how your RTL is coded.
The following will likely synthesize to a DFFR (DFF with active low reset)
always@(posedge clk or negedge rst)
if(~rst) q <= 1'b0;
else q <= q_next;
The following will likely synthesize to a DFFS (DFF...
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