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If you're reading the paper and asking us, either the author isn't explaining it or you aren't getting it. I wouldn't hazard a guess on such sketchy information.
It's certainly worth thinking outside the box on biasing, though. I used a constant current technique for a bipolar transistor, and...
I did a late degree of sorts and prototyped this in discrete hardware using 74AUC, with a 74AUC16374 (16 D flip-flops), so I have a hardware control strategy known to work that I can replicate.
My one remaining question is: How should I recreate in vhdl(for internal use only) an array of 16...
Thank you very much for your time and wisdom, gentlemen.
We did a vhdl module at University, but this makes me realize how lazy the guy actually was. Going for a substantial rewrite in line with criticism, as this code needs to be good, and timed well. That rewrite will be slow, as I am...
Stuck using Lattice isplever (with VHDL-93?) fo ispmach 4064V
My full code is at https://pastebin.com/Dc4mCFVc but here's the problem area
-- 70 The Above provides FM timing
-- Counting hbd(=pulse length)twice as fast as fm for 50% duty cycle.
if (rising_edge (clock)) then
if (hbd > 0)...
It's got a circuit to generate & discriminate FM/FSK using period measurement, and minor glue logic (H-bridge driver, switches read into logic, etc.). I haven't gotten around to implementing usb, or even thought about it. Early stages yet. If I could buy some IP, that would save effort. USB-2.0...
I am currently limited due to a stroke,. so apologies for misspellings.
I am trying to start on 3 uncomplicated projects, and initially need a CPLD (probably) with
200 Mhz
Less than 2 dozen I/O
Connect ideally to USB
Not going obsolete
Any ideas? I picked an ispMach4032, but Lattice...
With this stuff, I created a vm under virtualbox, installed barebones m$ windows(ugh!) and installed there. You need the extras. I had to marry a few partitions to create one big one for the vms.
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