Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by Brina9797

  1. B

    Synopsys IC Compiler: Open Nets Error

    Hi, thanks for the reply. I had managed solved the open nets error. However the message: " Total Floating ports are 1 and ERROR : OUTPUT PortInst h3/c2/presentstate_reg[0] QN doesn't connect to any net. " is still shown in the LVS report. The floating ports is pointing to the error (" OUTPUT...
  2. B

    Synopsys IC Compiler: Open Nets Error

    Hi, do anyone know how to solve the open nets ( Logical Net VSS is open) error? I obtained the error message attached below in LVS during final design checking.

Part and Inventory Search

Back
Top