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Recent content by brainiac_rus

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    [SOLVED] DPI and Questasim error

    I get some thoughts about it. I use win 7 x64 and may be for using C code questa needs c compiler, but in linux it is standard gcc, but in my windows it can't find it and can't do what i want. Is it true? - - - Updated - - - Yes, it is true! I forgot install gcc compiler to my system, but do...
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    [SOLVED] DPI and Questasim error

    Hello! I tryed to run DPI with Questasim. I saw topics about it but version of sim changed and some things could be changed too. My C code: #include <svdpi.h> //#include <gmodel_tb_top.h> int factorial(int i) { if(i <= 1) { return 1; } else { return...
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    [SOLVED] How to write constrain for spi interface

    I use AD5542A - it has maximum SPI speed 50MHz But in my design practice i get metastability on design with adc connected to fpga through isolator. And speed of that interface was 20 MHz, delay between clk on fpga net and miso net was about 26ns at worst case. I need to do my design more...
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    [SOLVED] How to write constrain for spi interface

    Hello! I want to write constraint for spi interface. FPGA is spartan-6 and i use ISE 14.7 Spi interface is the same as on picture. Clk line of SPI is the output of register. I want to write constraints for this interface. I tryed to write something: NET "Data 1" OFFSET = OUT 8 ns AFTER...
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    2 questions about xilinx edk and verilog

    Hello! First question is about using Xilinx EDK. I use it for implementing axi system with my cores. I don't understand next thing: if i design my core with axi interface and implement it to the axi system, than if i change this core - i think there are two ways - with or without changing...
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    deserializer and fpga - how to latch data

    Hello! I have a board with fpga spartan 6 and serializer sn65lv1023a deserializer sn65lv1224b. There is a channel between serializer and deserializer which can be work on speed from 120 to 720 MHz. In my case it works on 120 MHz. My problem is that there many errors in receiving packets, when...
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    [SOLVED] cordic calculations of sine and cosine functions in fpga

    Ahahahahaah!!!!! This is professional deformation!!! I started to think parallel as an FPGA))) Thank you so much!
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    [SOLVED] cordic calculations of sine and cosine functions in fpga

    No, this is wrong, because input angles are from -pi/2 to pi/2 and first angle which tg(phi) = 2^0, i.e. 45 degrees
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    [SOLVED] cordic calculations of sine and cosine functions in fpga

    Hi all! I tryed to calculate a value of sine and cosine functions using cordic algorithm. But it does not work in fixed point system and i wrote it as simple program. Here is a code: module cordic_test0( ); real cordic_iter[15:0]; real angle; integer i = 0; real xi; real yi; real zi...
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    [SOLVED] Writing to NAND Flash works correctly only after Erase. Is it a reality?

    Hello! I use in project FPGA and NAND Flash MT29F04G01 I developed spi core for this chip and try to read/write data from/to this Flash. There is a cache register, in which data writing first, and then transmiting in NAND memory array. In reading data transmiting from NAND memory array to cache...

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