Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by bossbebes

  1. B

    What should be the scope of my sdf file?

    Re: scope Hi , Thxs for your reply What do you mean by : "netlist is matched with your sdf file". First of all i generate a netlist (.vqm) with symplify_pro, then I genete the final netlist + delay (sdo, vho) thanks to quartus software. I guss that my netlist should matched with my sdf...
  2. B

    ncelab // synplify_pro // quartus // stratixii

    Hi everybody I m designing digital electronic entity to be place in an stratixii fpga. I m using synplify pro to compile my RTL level design, output file .vqm Then I generate a vhdl netlist with the quartus software + timing (sdo + vho) in order to simulate this netlist with simvision. And when...
  3. B

    What should be the scope of my sdf file?

    I everybody, I try to elaborate my gate level netlist and I can not find what should be the scope of my sdf file. My netlist is from quartus and I elaborate with cadence environment (ncelab). I have a test bench, made by hand : nce_tpc_tb.vhdl In this test bench I have : entity nce_tpc_tb is...
  4. B

    how to do post simulation with ncverilog?

    Hi, I would like to know what means SCOPE in the SDF file ? Thxs a lot
  5. B

    NC-Verilog post-simulation problem

    nc verilog library compiler And what about the scope in the sdf file. Do you know what should be this field ? What does it means? Thxs A beginner ....
See more

Part and Inventory Search

Back
Top