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Recent content by boshiouke

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    Why is it that in a cascode LNA, only the input transistor contribute to the noise?

    Re: cascode LNA Thanks for the reply, vfone. In CMOS LNA, since noise current is proportional to gm, the cascode transistor's gm is degenerated by input transistor, so I suppose that explains why it contributes less. But how about bipolar LNA? The shot noise is 2qI. How does it work over...
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    Why is it that in a cascode LNA, only the input transistor contribute to the noise?

    Why is it that in a cascode LNA, only the input transistor contribute to the noise, while the cascode transistor doesn't? Thank you.
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    RF measurement course from Besser Associates

    Can anyone that has attended Besser Associates' course in "RF measurement: Principles and Demonstration" provide some comments on the course please? Is the course useful, practical, or hands-on? Thank you so much. **broken link removed**
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    What's the tradeoff between VCO's start-up gain and its phase noise?

    Re: VCO TaimurSattar, Were you trying to say something? Boshiouke
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    What's the tradeoff between VCO's start-up gain and its phase noise?

    What's the tradeoff between VCO's start-up gain and its phase noise? Thank you.
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    How to simulate for charge pump leakage?

    Can anyone please show how to simulate for charge pump leakage? And what's the typical requirement on its amplitude? Thank you so much.
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    Charge pump charge sharing/bootstrap

    charge sharing charge-pump Would anyone please provide some materials that talk about the charge sharing and bootstrapping in a charge pump? Journal papers, books? Thank you.
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    phase noise simulation setup for PFD/CP

    pfd cp noise Does anyone know the difference between different "noise type" in Pnoise analysis, i.e "sources", "time domain", "modulated", when simulating for PFD/CP? I'd greatly appreciate it if anyone can show me how to set up the PNoise analysis for PFD/CP using those different "noise type"...
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    Questions about linear range of PFD

    linear range of PFD Is there a normal value for the linear range for PFD over a 4*pi span, say 70% or 80%? Or is it strictly a relative term as long as it can satisfy the frequency acquizition time requirement? As far as I know, the closer to 4*pi the linear range, the faster the PLL can...
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    Necessary simulation check for PFD/CP?

    Thanks once again for the input. In Wolaver's PLL book p.63, he mentioned PFD in high frequency operation, in which he talked about maximum useful frequency for a PFD, minimum duration of State 2 for a tristate PFD and maximum phase within the linear range. My question is, for a PFD to be...
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    Necessary simulation check for PFD/CP?

    Thanks again. I'm just wondering, if a PFD/CP works fine w/o dead zone @ 30MHz, is there any reason that it might not work or run into dead zone issue @ 30KHz? Besides, I'm not sure if I got the answer to my previous question, which is "the upper bound for the reset delay"? Thanks a bunch!
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    Necessary simulation check for PFD/CP?

    Got it! Thanks a lot. Btw, once a PFD/CP works @ 30Mhz Fref, for it to work @ much lower frequency, say, 30KHz, the width of the reset pulse should be made wider accordingly, correct? But, what's the implication of a longer reset pulse? Is there a rule of thumb for a proper reset pulse...
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    Necessary simulation check for PFD/CP?

    Thanks again for the reply. My question is, isn't it true that you actually NEED to have certain amount of current pulse at charge pump output @ zero phase difference for the PLL to work? If the answer is yes, then doesn't that mean that in the CP current vs. ΔΦ plot the curve should NOT cross...
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    Necessary simulation check for PFD/CP?

    Thanks again for the reply. I do have a question about the plot of CP current vs. phase difference. Is the curve supposed to be symmetrical against both x and y axis? If not, what does that say about the design? Besides, when the phase difference is zero, is the average integrated CP current...
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    Necessary simulation check for PFD/CP?

    Thanks, rfsystem. I've read quite a bit of your postings on PLL/dead zone, and they're quite helpful. Let me make sure I understand. So basically once the dead zone issue is taken care of by sweeping input phase difference, the simulation for PFD/CP is pretty much done. Is that correct? Well...
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