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Forgive me if I am wrong but is GDS not only used as an output file to give to the foundry? Sorry, I'm merely a graduate student working in a IC lab and Im not as familiar with these tools as a professional. The design in question is still a work in progress so I need to keep it in a file format...
I'm having an issue with a design I am working on in Cadence IC 6.1.6. I have a design where I am trying to use the space based router (VSR) to route my interconnect. It works fine and I get no DRC or LVS issues but my layout.oa file size seems to nearly tripple in size. Now, the file size isn't...
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