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Hello,
I'm designing an Opamp in 0.18u process using Cadence 5141. I have some questions, can everybody help me please:
First, about the supply voltage: my opamp have the supply voltage of +/- 1.8V. Is this too small in Opamp design or it is acceptable? Because I know that the typical value...
Thank u, evilguy.
I want to design mixed signal. An 8-bits integrating (dual-slope) A/D converter. In this design, there are analog parts (integrator, comparator, bandgap voltage reference) and digital parts (counter, latch, register, switch,...)
I'll try your way 'cause it's really difficult...
to raduga_in: I have read your document and have found some books such as: CMOS Logic circuit design [John P.Uyemura, Springer]... It's really complicated to design multi stage digital circuit in CMOS process.
I'm just starting with analog design and I don't have so much time for this...
cmos logic
I'm using General PDK, but unfortunately it's don't have digital standard cells.
I hope that everyone will give me some other advices. Thanks alot.
minimum size inverter for 0.18u cmos process
Hello,
In my design there is the Digital control part, so I want to ask about digital design in CMOS 0.18u process. I'm now using Cadence 5141. How about the W and L when we design logic gates such as: inverter, NAND2, NAND3, NOR, XNOR,... and...
cadence cannot initialize wavescan
Sorry that I come back too late. I have solved this problem by chosing the default plotter (AWD).
-- To chose AWD: in the Virtuoso ADE window, chose Session/ Options/ Defaults and Apply.
Then everything very well. My simulation have good result.
Thank you...
unable to initialize wavescan
Hello,
When I run the simulation of a current mirror, it's take error and this message appears in CIW:
*Error* Unable to initialize WaveScan. Please exit work-bench and try again.
*Error* Unable to establish connection with WaveScan. Please exit and re-start...
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