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Recent content by bm.iitkgp

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Virtex II Eval board - Help

I think the following link can be of help to you: **broken link removed**
- bm.iitkgp
- Post #2
- Oct 30, 2005
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
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Need documents about timing recovery and carrier recovery

Re: need help perhaps these links can help you: http://bwrc.eecs.berkeley.edu/Research/IC_Design_Flow/Theses/phusted_masters.pdf **broken link removed** **broken link removed**
- bm.iitkgp
- Post #2
- Oct 30, 2005
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
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Digital Hardware Design: Book advice request

Digital Integrated Circuits...a Design perspective...Jan.M.Rabaey...Anantha Chandrakasan...pearson education...
- bm.iitkgp
- Post #9
- Oct 30, 2005
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design

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