Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
dynamic zero ldo
I am new to this LDO area, and was trying to get some practical insights into deciding which is the better way of having the dominant pole at the LDO output or dominant pole generated internally. The application is for cellphone PMIC (Power Management IC) where there are 14 to...
From what I read, the absolute value of a CMOS bandgap using substrate PNP is affected mainly by mismatch in the PNP. op. amp. offsets, current mirror mismatch, resistor mismatch. If the circuit is well designed, large W, long L, wide R, and well layout. What is the absolute variation in the...
ldo bypass cap
I am new to LDO designs, just did some reading up. Not clear about the practical choices of LDO with or without using external bypass capacitor.
A) Without external bypass capacitor, internal dominant pole
Pros: cost saving of the external bypass capacitor
Cons: 1) Need internal...
pfm circuit
I have subscription to IEEE Journal of Solid-State Circuits. There are a number of references on PWM circuit designs. However, I was not able to locate much reference on circuit design for the PFM (Pulse Frequency Modulation) used in switching regulator. I am aware of the paper and...
ldo without capacitor
I am new to LDO designs, just did some reading up. Not clear about the practical choices of LDO with or without using external bypass capacitor.
A) Without external bypass capacitor, internal dominant pole
Pros: cost saving of the external bypass capacitor
Cons: 1) Need...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
