Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by blitzwing

  1. B

    How can i realize that the FPGAs configuration is completed?

    Re: How can i realize that the FPGAs configuration is comple I think you can but if I were you I would at least add some delay for the reset signal.
  2. B

    How to make a circuit on FPGA to run exactly at 2^28 MHz?

    fpga+clock I am using the FPGA beacuse I have the circuit in it. The 250 Mhz is the maximum operating frequency of the FPGA's PLL. The circuit can run with a clock up to 400 Mhz. Propably i wont be able to run at that exact frequency so I guess I'll have to change the design a little bit...
  3. B

    How to make a circuit on FPGA to run exactly at 2^28 MHz?

    how to use clock in fpga FINALFANTASYFAN as I said I will propably use an external PLL. The external PLL can provide the exact frequency(2^28MHz)?
  4. B

    How to make a circuit on FPGA to run exactly at 2^28 MHz?

    hi I have some questions. I have designed a circuit (schematic editor) and I load it into an FPGA (Cyclone II). The problem is that I want the circuit to run exactly at 2^28 MHz = 268.435.456 Hz I cannot use the FPGA's PLLs since their maximum output frequency is 250MHz. I was thinking using...
  5. B

    Help me find the VCO for a CPLD

    Re: Clock input CPLD echo47 I live in Europe and i cant find anyone to give me a fixed-frequency crystal oscillator (XO). I thought VCO and XO where the same sorry. I'm trying to avoid digikey for now beacuse the cheapest shipping fee for Greece is about 40$.Farnell which is in UK doesnt have...
  6. B

    Help me find the VCO for a CPLD

    Hi i have designed a PCB with a CPLD on it and i am really having trouble finding VCO(voltage controlled oscillators) for the CPLD. I want to feed the CPLD (Max II) with a clock 10Mhz. Isn't any other way to avoid using a VCO. I have seen different schematics for CLPD and FGPA and they all use...
  7. B

    FPGA - multiple pulse generator

    fpga pulse generator Hi all I am trying to make an FPGA produce from its IO pins pulses with duty cycle 50%. The frequency of the pulse must be able to change it from 1 Hz to 10-15 Mhz with a step 1 Hz. I have used accumulators to accomplish that. (Idea taken from DDS). I dont care to make...
See more

Part and Inventory Search

Back
Top