Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
I have found a partial solution to my problem. It looks like the
"set_app_var hdlin_sv_blackbox_modules {moduleNames}" command marks a module such that DC no longer includes an empty module definition (problem #1 above).
However, DC still removes the parameters (problem #2 above), now...
I have a parameterized Verilog module foo that I would like to black box during DC synthesis and be able to plug in a simulation-only module later on. Essentially, whenever I've instantiated foo in my design, I would like DC to pass these instantiations (with parameters) through to the mapped...
Looking at the source .lib in more detail, I guess my question is why doesn't Design Compiler pick up and use the "timing_type: minimum_period" constraint? I've tried modifying the "when" and "sdf_cond" parameters to see if it would help the behavior of dc_shell, but this doesn't seem to work...
I'm new to Synposys DC and I'm having trouble with timing analysis. Basically, I've got memories generated through TSMC's mc2-eu tool. Looking at the output .lib and simulation Verilog, they seem to be reasonable blackbox units. However, when I instantiate them and define/constrain a clock...
I figured out what the problem was. These two modules were in two different files and I was using the "file_read" command to bring them in. File_read performs both analysis and elaboration. Elaboration was tying the parameter to the default value for the child, so when the parent was...
I have parameterized Verilog that works in Quartus and Modelsim, but I'm having trouble getting it to work in Design Compiler. Basically, the issue is that if I instantiate a module with parameter other than the default value, I get the problem:
Information: Building the design 'child'...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
