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Recent content by bking

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    Power Supply Design for timer application

    How much current? What input power is available? The 7805 requires at least 7 volts in to regulate to 5 volts, so we know you need at least that. How about just using a 9 volt battery?
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    [SOLVED] Take different output value from array every clock cycle

    I would have thought you would get a multiple driver warning, but we can't see all of the code. Your problem is you are writing this as software. A FOR loop doesn't loop like software, it's a shortcut for typing. Search for "VHDL FOR LOOPS" and you will find many examples of how to use them. To...
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    Warning Altium Designer 18

    See here It looks like an issue when using differential pair routing. It was fixed in 18.1.6. At least upgrade to the highest ver. 18 that you can. Altium just announced release of Ver. 20.
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    2:1 Multiplexer with open drain Outputs IC

    Hmm... I didn't have the post with the picture until now. I see you also flipped it to a 1:2. How about a 74LS156. That has open collector drivers.
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    2:1 Multiplexer with open drain Outputs IC

    How about something like this: https://www.onsemi.com/pub/Collateral/NC7SZ157-D.PDF Looking at the datasheet, the switching thresholds are 0.7 for H and 0.3 for L, so as long as your input levels can swing beyond those points it should work.
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    Difference of LVDS, LVPECL, HCSL, LVCMOS

    This has an overview of levels: https://www.ti.com/lit/an/slla120/slla120.pdf This data sheet has a table of thresholds and levels: https://media.digikey.com/pdf/Data%20Sheets/SiTime%20PDFs/SIT9102A.pdf
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    Identify capacitor with marking code L62 104

    The 104 is a 100nF / 0.1uF. The caps are typically marked with the first two digits significant and the third digit indicates # of 0's to follow. The L62 may be a lot # / date code for a manufacturer or some other parameter info coded by the manufacturer.
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    [SOLVED] FPGA Kit Recommensation

    Re: FPGA Kit Recommendation From your attached report, you had already selected a device otherwise it could not have know the percentages. What was that one? Once you find that you can then see what is offered in that family. The info in the table is only relevant to the same family of parts.
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    [moved] Lattice CPLD Reconstruction and porting

    Xilinx's ISE webpack or some other stand-alone tool has a tool for converting ABEL to VHDL (and probably Verilog). It just happens that I used it for a Lattice CPLD as well. It flagged hardware specific things that weren't generic (in my case I think they used dedicated shift registers, it's...
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    Motion Detector Alarm Timer Modification

    Normally the motion senor is connected to an alarm panel that will respond to the temporary activation of the relay and latch the alarm. It seems like the OP is looking to avoid the panel entirely and trigger something for longer than the motion activity. A delay relay might fit the bill here.
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    XC9536XL programing by DLC9G

    Since you have checked the voltages I'll ask the most obvious question - are you calling out the right part / using the correct bsdl file? The part where it asks if version 0101 is supported could be an out of date bsdl file vs. the programming software. Try downloading the latest bsdl file from...
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    Spartan-6 Servo Control

    Have you tried checking the signals to the servo with a scope to see if they are there? Are you using the correct pins on the header? Also, search for info on using clock enables with one clock (or few clocks) instead of dividing clocks and trying to use those (your "temporal" signal). The...
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    Variable gain through a microcontroller

    The AD5290 will accept +/-15V supplies.
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    Information about a device

    If you didn't know what it was, why did you buy it?
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    Modbus Communication circuit

    Are you providing the Common connection on the isolated bus side? That would be the GND2 in your schematic. On the non-isolated version you are likely picking it through other means. When you try the isolated version, if that's not there you have no common mode reference point.

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