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Recent content by bits_dude

  1. B

    Hi...is there any one working in cadence RTL compiler

    What doubts u have?
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    what is time scale in veilog, defines and why it is used for

    Re: Time scale in verilog Thanks dude... nice example !
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    multicyle and false path in asic Design

    design compiler multicycle Can somebody tel me how do I decide on multicycle path ? Lets take an example: I need to derive constaints at the top level ( chip/SoC level) I have a path running from one IP-block to another IP-block then how do I know that this path is a multicycle or not ? Thanks.
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    actors on which a FLOP's setup window size depends on

    FLOP's setup window size Hi Everybody ! What are the factors on which a FLOP's setup window size depends on? Thanks, bits_dude
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