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Recent content by bill_sun

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    MOS & MOM combination layout

    We also prepare to do this these days.AFAIK,the DRC rule will not be met. Of course it will be OK when testing the chip .But the reliability would be a problem in the future .
  2. B

    What is a clerk's salary in China?

    Working in CHINA It depends on which firm u are working in.Intel ,TI or some tiny ones?
  3. B

    how to estimate the settling time of vco?

    nobody knows this??? Any advice will be welcom.
  4. B

    how to estimate the settling time of vco?

    Usually an initial volt. or a current pulse which models the effect of noise is set at the beginning of simulation.In this way we can get an estimate.But is it accurate enough?Is there any other method which is suitable for hand calculate??? Thanks.
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    div-3 divider with 50 percent duty cycle?

    Thx for yr help.yes,it's really a challenge for me.I would design a wideband lcvco with a calibration module to adjust it.
  6. B

    div-3 divider with 50 percent duty cycle?

    The background of this question is that we need a differential clock ranging from 100Mhz to 750Mhz with low jiiter(rms jitter is less than 1ps).The ducy cycle is 50%.The ring VCO is easy to cover this range,but the jiitter is too high.So the LC VCO is selected for this application.As you...
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    div-3 divider with 50 percent duty cycle?

    hi guys,do u have any suggestion to me? operating freqency:3GHZ;differential signal;50% duty cycle; SCL is impossible to get this. Any advice will be welcome.
  8. B

    How to simulate different block of PLL for noise ?

    Re: PLL noise simulation search the direction in which Cadence is installed,find it and add it in yr cds.lib it's written in verilogA and can only do behavior level sim.
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    ring oscillator frequency variation

    it depends on yr spec.In low cost consumer elec. a vco wo a pll is enough.
  10. B

    Two Questions about Ring Oscillator

    A noise file of the supply off chip can be written and added in yr simulation schematic .Runnig PSS AND PNOISE would show u the noise curve .
  11. B

    How to simulate different block of PLL for noise ?

    PLL noise simulation Cadence can do this too using the cells in lib "pllLib"
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    what is hot topics in analog design research?

    every tradional ckts would all be researched and designed again in nano period.There're so much challeage in it.
  13. B

    Simulate VCO using Cadence

    simulating vco yes,it's a perfect tutorial.suitalbe for freshers.

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