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We also prepare to do this these days.AFAIK,the DRC rule will not be met. Of course it will be OK when testing the chip .But the reliability would be a problem in the future .
Usually an initial volt. or a current pulse which models the effect of noise is set at the beginning of simulation.In this way we can get an estimate.But is it accurate enough?Is there any other method which is suitable for hand calculate???
Thanks.
The background of this question is that we need a differential clock ranging from 100Mhz to 750Mhz with low jiiter(rms jitter is less than 1ps).The ducy cycle is 50%.The ring VCO is easy to cover this range,but the jiitter is too high.So the LC VCO is selected for this application.As you...
hi guys,do u have any suggestion to me?
operating freqency:3GHZ;differential signal;50% duty cycle;
SCL is impossible to get this.
Any advice will be welcome.
Re: PLL noise simulation
search the direction in which Cadence is installed,find it and add it in yr cds.lib
it's written in verilogA and can only do behavior level sim.
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