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DC should analyze timing on the worst case events on those start/end points, whether it's a pin or port. Overloading the port constrains with virtual clocks may introduce timing events that may not represent the actual operation of the design.
I recommend researching set_clock_groups to...
I'm guessing that the Verilog file, {../../dc/output/compile.v}, does not list the definition of the module, DFFSSRX1_RVT.
You would have to locate the definition of that module append/include that in compile.v.
The module definition would eventually lead ICC to initialize that "_RVT" design as...
It sounds like you would have to create those clocks in the design yourself, most probably by dividing down the original clock twice in a cascaded fashion, to generated CK2 and CK3.
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