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Suppose I write 700 datas initially and then starts reading so that FIFO will not become empty. I continue writing datas along with read too. Then?
In such a situation, there is a possibility that my read pointer - write pointer comparison will go wrong, right?
Hi,
https://www.edaboard.com/showthread.php?197207-FIFO-read-amp-write-pointer-synchronising-for-asynchronous-FIFO
The mentioned link in this forum explains how read pointer comparison with write pointer in an async FIFO will not create any problem even if the read pointer is incremented...
This is an interview question I found:
I have three clock domains A, B and C.
I have some data coming from clock domain A and clock domain B.
I want to do some combinational operation and send the resulting data to clock domain C.
How can I do this?
We normally use RAM for FIFO implementation saying Flip flop implementation is costlier. How is RAM memory implemented in hardware? If RAM is implemented using normal flip flop registers, what is the use of using RAM? How RAM implementation becomes cheaper than Flip flop implementation?
What I understood from the internet is that, since ARM architecture is based on RISC model, the complexity of hardware is less compared to that of Intel which follows CISC. The simple hardware reduces power consumption.
But my doubt is that, in RISC architecture, when the hardware complexity is...
ARM processors dominate over Intel processors in mobile phone markets because of it's power efficiency compared to Intel. How does ARM processor achieve lower power consumption compared to Intel for same operation? For example, consider the case of multiplication between two numbers. How does...
I am a hardware engineer (RTL design) and I don't write microprocessor codes. Yea, I should be knowing what microprocessor is being used in my system. But to design RTL, knowledge on the microprocessor family is not a mandatory infomation.
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Yes, you are correct on this. I...
Hi all,
Thank you all for the responses.
This was not a hypothetical question and the question was based on a bluetooth system I work on. I don't know which microprocessor family is being used in the system, but the ISR is executed based on negative edge of the interrupt line.
In our scenario...
Hi,
Usually, an interrupt is generated by the hardware in a design and the processor reads the interrupt when a negative edge is detected at the interrupt line (assuming active low interrupt line). After the firmware reads the interrupt line and execute the ISR, it will clear the interrupt...
In this case, we are delaying P by 1 clock cycle, right? Suppose this P is used at some other part of the design. Won't this break the existing logic? Or you mean to say that, while applying pipelining, we should be taking care of this situation also?
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Please see my above...
There are many posts that deal with setup and hold violations and their fixing in backend stages. Suppose that the initial synthesis itself gives setup and hold violations. What are the possible methods to fix them in RTL?
I could find following suggestions in some of the posts. But how...
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