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Recent content by bigyellow

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    A question about Modelsim Waveform

    In my DO file, I want to write some script to detect if there is any active waveform window in Modelsim. Are there any modelsim commands that I can use to do that?
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    Can I use clock with frequency lower than 125 MHz for DDR2 ?

    DDR2 clock frequency because I have system clock in this frequency, if I could do this, this is the easiest way.
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    Can I use clock with frequency lower than 125 MHz for DDR2 ?

    Hi, As we know, in principle the DDR2 requires at least 125MHz clock frequency. Is it a problem if I use a clock which is a little slower than 125MHz, say 122M-124M?
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    Does modelsim support systemverilog simulation now?

    systemverilog in modelsim if so, which version? thanks.
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    The filename extension of systemc

    Hello, In systemc, what kind of files should be named as *.cpp and as *.h?
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    Questions about SystemC syntax/support

    questions about systemc 1. Is this syntax correct, a is a bool type variable, and b is a bit_vector type variable? a = b.range(15,0).and_reduce(); 2. Does Modelsim support the mixed-simulation with system-c and VHDL/verilog, for example, testbench is written in systemc and DUT is written in...
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    If I instantiate Altera PLL to LVDS mode can I reconfigure the LVDS clock output freq

    I have a question about altera PLL, if I instantiate a PLL to LVDS mode in stratixII, is it possible to reconfigure the frequency of LVDS clock output(sclkout) on-the-fly? thx.
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    Sync Reset or Async Reset

    asyn, use reset synchronizer to avoid metastability
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    Why many EDA vendors use TCL/TK to develop their EDA tools?

    Re: Why use TCL/TK? why use Tcl/tk, rather than other script language, e.g. perl. python, shell......
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    I wang study SystemC,are there any examples for primers .

    There is a book called "A Systemc Primer", U can download it in this forum.
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    SystemC to GDSII !is it a dream?

    I think SystemC is hard to be accepted by industry, especially in ASIC design. There are a lot of risks and cost. For example, convert system level SystemC codes to synthesisable SystemC code aslo need some work. Company aslo need defined new coding rules for synthesisable SystemC code, systemC...
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    Do we need Matlab as an ASIC designer ?

    I think in the system modeling e.g. telecommunication system, matlab is widely used. And also generates test data for verification .
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    SystemC to GDSII !is it a dream?

    Well. I think SystemC will have good future in academic. But hardly accepted by industry.
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    SoC system level simulation

    I think systemverilog and VHDL 200X will be the future.
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    SystemC to GDSII !is it a dream?

    I think SystemC is hardly accepted by industry recently. especially in RTL and lower level. It is far from the vhdl and verilog. I think systemverilog and VHDL 200X may be better.

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