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The signals from router to the memories are all separate and registered.
Even in the timing report, I see only two entries in the path, WR_ADDR_REG(my signal) and asyncram address register.
There may need to be internal duplication required, but I can't control it. Each bank is 64 M20K...
I am using Quartus and Stratix V.
I have a design that has 14 memory banks. Each bank is 64xM20K blocks.
There is block (MUX) that reads/writes one bank, while another block (FFT) that reads/writes another bank.
There is a 1 to 14 registered router between the blocks and memories.
The clock...
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