# Recent content by bigdog

1. ### How to deal with gated clock in Synopsys Formality?

I used DC to compile the design and dumped the svf file too, after Formality reading the svf file, it wrote a file(svf.txt) that contants the statement "guide_environment \ { { clock_gating latch_and } }", so I don't get the reason why Formality still doesn't pass the verification.
2. ### How to deal with gated clock in Synopsys Formality?

Hello, I compiled some gated clocks in my design, and when I do formal verification, the gated clock cells are in unmatch cell list, how can I tell Formality about the gated clock setting? Regards,
3. ### How to get off some cells like "**SEQGEN**" in DC

Hello, I want to compile my design to gate-level with DC, but I always got some cells like **SEQGEN** in the netlist, I have no idea about the reason, that seems like I didn't finish the compiling, is the anyone knows that? Regrads,
4. ### How to stop simulation in VHDL testbench?

Hello Devas, Yes, the statement works! Thanks a lot! Regards,
5. ### How to stop simulation in VHDL testbench?

Hello, I don't know how to stop my simulation, my testbench is described in VHDL and I use ncsim, is there any method to stop the simulation just like using $stop,$finish in Verilog? Regards,
6. ### clock multiplexer problem - help needed

clock multiplexer Ok, thanks, I'll try that.
7. ### clock multiplexer problem - help needed

Re: clock multiplexer If I do so, how do I to do the timing analysis with PT, should I set case analysis since I have a multiplexer on the clock path?
8. ### clock multiplexer problem - help needed

clock multiplexer Hello, I have two input clocks, CLKA and CLKB. They go to a multiplexer directly from input port then generate a new clock CLK_SYS as the system clock of the whole circuit, but the select signal of the clock multiplexer comes from the CLK_SYS domain and its value is not a...
9. ### Constraint on Multi-Clock with a same source

Since the definition of the two clocks are separately, and the frequency are different too, so how to tell DC that the two clocks have a same source?
10. ### Constraint on Multi-Clock with a same source

Yes if I have the whole circuit, the key is that CLKA and CLKB are all input clock, so I can't do that ..
11. ### Constraint on Multi-Clock with a same source

Hello guys, In my design, we have multiple clocks with different frequency, but the clocks have the same source. (For example, clock A and clock B both are divided from clock S, and Frequency(A) = n*Frequency(B), n is an integer) There are some logic between the two clock domains, how can I...
12. ### Constraint on combination logic in DC

set_max_delay Well, I think your suggestion is right, setting constraint like that will not get any vioalation. Thanks!
13. ### Constraint on combination logic in DC

set_output_delay in dc Hi all, I use Synopsys DC to compile my design, and in the design: A is the input, B is a sequential logic output of it, and C is a combinational logic output of it. In my constraint file, for sequential part, I set constraint like below: create_clock -period 20 -waveform...
14. ### DC_SHELL constraint about input delay and output delay

input delay Ok, thank you so much! Best regards,
15. ### DC_SHELL constraint about input delay and output delay

input delay and output delay Hi Guys, I am confused with the command "set_input_delay" and "set_output_delay": The clock frequency is 50MHz. For constraint on a path from input pin to a DFF, I want the logic between input pin and the DFF to take only 5 ns, should I use "set_input_delay -max...