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Recent content by bibo1978

  1. bibo1978

    Iso 7816. PDF files plz

    I changed the original request accordingly ---------- Post added at 09:43 ---------- Previous post was at 09:42 ---------- Thank you for your advice
  2. bibo1978

    Iso 7816. PDF files plz

    I am asking for a Draft which is not a copyrighted document
  3. bibo1978

    Iso 7816. PDF files plz

    Can anyone help me with the full specs of ISO standard 7816-15 a final draft PDF (not copyrighted)
  4. bibo1978

    C Programming for Playing Vedio or displaying image

    This is a very generic question, C programming on What? is there OS on the system? C programming means a compiler, an IDE and libraries and output assembly code that will be rendered, generally speaking it is totally different to produce a binary file that will work directly on a processor, that...
  5. bibo1978

    clock domain crossing

    how does grey code help async clock crossing I don't understand your question however I will add a note, that might answer u, the metastability filter (two FFs usually) diminish the probability of metastability propagation, which might cause circuit failure, metastability might also cause...
  6. bibo1978

    communication problem between two FPGA board through UART

    UART -help Well I can give you some guidelines, first of all of course you will put the regular two FF (metastability Filter), then some switch detection circuit, i.e. a circuit which will determine if data changed from zero to one, you logic must work at at least double the clock speed...
  7. bibo1978

    clock domain crossing

    grey code in clock crossing domain Guys, if you read wrong data this doesn't mean metastability ... ! just simply according to any logic data should be sampled at some specific time (hold period) which is managed by passing the clock. when you read data Bus Asynchronously you may get wrong...
  8. bibo1978

    circuit for a Async to Sync converter, using a AVR micro

    Async to Sync Well it depends on the data rates, Like UART, a start and stop bit is enough, you can sample the data at double the speed or more, using a technique to aviod metastability a lot of techniques out there and a technique to detect 0-1 transition. At very high speed Async data you...
  9. bibo1978

    clock domain crossing

    crossing clock domains + digital design Bottom line use Async FIFO
  10. bibo1978

    clock domain crossing

    how is appalix 1-synchronizer is used to decrease the probability of metastability not to allow it! 2-One bit is not data it is a signal if you want just sample it directly you will only have a more probability that ur circuit fail or hang or read wrong data for a longer period of time you need...
  11. bibo1978

    clock domain crossing

    metastable clock domain crossing ASIC_int 0101 is not a metastable state, when you read 0101 usually means that data was read on its transition state but since you read some value then you read right the problem mainly is that value that you didn't reach metastable state. If you read data bus...
  12. bibo1978

    clock domain crossing

    double flop synchronizer book guys metastability is not that you read wrong data it is that your circuit might work in non descrete mode simply your FF is more or less some transistors they are designed in such a way that it will usually be saturated or switched off (on-off) however there is...
  13. bibo1978

    Issues in using xilinx primitives to generate delay elements

    xilinx delay function J_andr I dont say that tricks will not work and it is ok to do so and I have done this actually in some ciruits you can't get some data except with a delayed pulse" like DDR DQs" but you can't get a delayed clock this way and if your pulse route is big or it drives more...
  14. bibo1978

    Issues in using xilinx primitives to generate delay elements

    xilinx synthesis issues First of all I wouldn't do such a delay ever, it is inreliable and a Buf object is not routed to the global clock network and you can't use a BUFG to delay a clock, use DCM for delaying a clock Anyway I think the problem is in the resolution you are using in the...
  15. bibo1978

    clock domain crossing

    problems connecting to domain as clock incorrect FIFO is used when you need to transfer data from one clock domain (clock domain at which you store data) to another clock domain, it grantees that the data will cross from that domain to the other (smoothly) if the Asynchronous FIFO is designed...

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