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Recent content by bhaskarskj1

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    Full adder with 3 input signals (vectors)

    hi Rorsh14, why are you go for complicated thing, no need to write unnecessary components. check top level modified program entity full_adder_3bit_12bit is Port ( a : in STD_LOGIC_VECTOR (11 downto 0); b : in STD_LOGIC_VECTOR (11 downto 0); c : in STD_LOGIC_VECTOR...
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    FSK Modulation in VHDL

    hi vijay vinay, use loglk is shift register,take single bit out, you can easily solve the problem
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    can u help me?

    Hi Don't use same signal in two process statements, both process statements are concurrent it will be operate at a time. use one process is enougham for this program
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    How to create our own IP Core

    what is IP ?
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    problem in executing

    initialize the integer values and use delays in process
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    Advice regarding a RISC course or a book

    Hi ammar_kurd, 1. What purpose you need risc process 2.8 bit processor/16 bit..... 3. clock speed 50 Mhz/25 Mhz... 4. No. of instruction sets (addition, sub, increment, dec.....) 5. alu depth 6.Any other additional features Search in google for different Risc processor designs, finalize...
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    Advice regarding a RISC course or a book

    Hi, go through google u get lot of risc and mips processor but what is your risc processor specifications, thanks and regards bhaskar

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