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Recent content by bharundi

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    Which one is good for performance - Packed Array or Unpacked Array

    Good to know. I was lazy and wanted a quick answer; I think I can produce my own numbers. :)
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    Which one is good for performance - Packed Array or Unpacked Array

    Thanks Dave for your suggestions. Though, it is not my primary concern (as this is mainly used for DUT<->TB interconnects), I do agree with you on the first paragraph. Good to keep in mind. The rest of your suggestion is appealing to my needs, and it does make sense. I also don't have a...
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    Which one is good for performance - Packed Array or Unpacked Array

    Hi All, I have a performance related question here regarding packed array vs. unpacked array. I am trying to determine which one would give better performance in terms of simulation using one of the following simulators: -- Synopsys VCS -- Mentor Graphics Questa -- Cadence IUS Note, I...
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    [SOLVED] Using VCS to compile SV filel ist

    Can you show the complete command line and the error message? Does the message report a problem on the filelist or a source file included in the filelist? Are you using any environment variables in the filelist?
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    what is the significance of Seed value for RTL simulation ?

    Take a look at https://en.wikipedia.org/wiki/Random_seed If the testcase (and/or other parts of your testbench) run against your DUT is random, then it can generate a different set of stimuli to the DUT on a different seed. We can't definitely say it is a DUT bug, as it can happen to be a...
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    SystemVerilog Clocking Block

    The frequency of cb will inversely propositional to the time unit of the module or block. If the time until is 1ns, then the frequency of clk is 100MHz, hence triggering/sampling of the cb block occurs at every 10ns. That is because "posedge clk" is used as the clocking event. When you use...
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    Configuration using $value$plusargs

    Can you elaborate what you mean by "this statement does not work"? Does it not compile? Does it not grab the value for its corresponding plusarg? I see a syntax error in the pointed statement. The following will work. Also make sure that the fencer_tx_fc array exists (i.e. array size is...
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    Dynamics and elaboration in Verilog

    This is where things start to get gray. Here are my best attempts to answer your questions. 1) I am not very familiar with all of the tools you mentioned here, but generally any tool wanting to make sense out of the design (and/or environment) has to go through some, if not all, stages of the...
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    Need of good sta tutorials

    Following document posted on a LinkedIn group discussion: https://docs.google.com/viewer?a=v&pid=explorer&chrome=true&srcid=0BwEyy2B_UVS2MDhkNmMzYmQtZmM3ZC00ODRjLWFmN2EtOTIxYzAwMTNkZjNi&hl=en_US
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    Dynamics and elaboration in Verilog

    A compilation process generally has three phases - analyze, elaborate, and link - to build an executable (before simulation can be performed). In the elaboration phase, the compiler (i.e. VCS, NC-Verilog, ModelSim, etc.) expands the elements (Verilog code) under generate statements with the...
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    What are the differences between dual-port and 2-port SRAMs?

    I recently heard a usage of dual-port and 2-port SRAM terms, but I wasn't quite sure about the differences. My impression had been that both are same, and the terms are used interchangeably. But, now I am thinking it's not true. I would appreciate any clarification anyone can provide on this...
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    Randomization of Array Of Objects in System Verilog

    When 'randomize()' is invoked on an object then 'randomize()' is also invoked on all of its 'rand' elements (after the end of its post_generate() but before returning to the caller) given that any custom types (objects, non-standard data types) are properly instantiated (newed) before hand...
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    I want to learn STA from basics

    I would suggest you to refer to https://www.amazon.com/Static-Timing-Analysis-Nanometer-Designs/dp/0387938192 This book covers materials from very fundamental to advanced giving particle examples (i.e. tool related).
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    From where we can get well-defined ASIC design flow?

    I would suggest Digital Integrated Circuit Design by Hubert Kaeslin. It is very informative. https://www.amazon.com/Digital-Integrated-Circuit-Design-Architectures/dp/0521882672/ref=sr_1_1?ie=UTF8&qid=1250021108&sr=8-1
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    verilog task and event

    task in verilog Make the event global so you can use it in the task without passing it as a parameter. Then optionally use a macro/define if it involves hierarcy path.
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