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Thanks for replying..
That is ok...
raj can u explain me, exactly how to measure the swing in simulator(ELDO), What is the input frequency i have to consider?? and does the swing anywhere related to the Harmonic Distortion???
What is the typical THD does an op amp can have???
But, insertion of one more stage leads to the need of compensation and the other parameters like UGB, PM may change...
If i insert a classAB stage, then will there be any problem???
waiting for reply.
Thanks & Regards
Thanks for the reply raj.
But i do not have time to redesign with folded cascode. All the parameters were ok, except swing and the slewrate.
My design results are as mentioned above and apart from that Settling time of 4nsec to reach 1 % of final value,
Any suggestions to improve swing and...
how to improve on an op amp
i have designed a fully differential op amp. Op amp is designed with telescopic gain boosting topology.
It is designed for 1.8V single supply in 0.18um technology.
which is having ICMR of 0.48V (0.65V-1.13V), and UGB of 1.06GHz, DC gain of 116dB, PM of 61degrees...
measuring slew rate fully differential opamp
I have designed a fully differential op amp. I do not know exactly how to measure the slew rate for a fully differential op amp. Generally for a single ended op amp we connect the op amp in non inverting(feed back) mode and measure the slew rate.
many to one mapping in schematic driven layout
i have designed an op amp..
now i wanted to draw layout for the op amp.
since there are many transistors present in my design i want to go for SDL(schematic driven layout). i m using mentor graphics ic station for layout design. i am able to place...
U can watch all the parameters by simply clicking on the component after performimg simulation. This is according to simulator.
If u want to calculate theoritically fix the W/L, Id, Vg and Vd and calculate µCox..
I designed my circuit in Mentor graphics. Now i want to draw layout of my circuit. I can use mentor graphics otself to draw layout, but i dont have permission for that.
I have licence for cadence to draw layout.
Does any one knows...
Re: transistor sizing
First of all can u tell me what is your circuit???
As i know
In cadence u cant go beyond 50um for W or L.
Anyway L is in the range below 50um.
and if u want W to be greater than 50um u can play with No:of fingers and multipliers.
W=No: of fingers *...
Thanks for your reply diemilio
I do not want to shift the noise from low frequencies to high frequencies(I mean in UGB range). I think that is not a good solution.
And redesigning may be a choice. So what are the precautions i should keep in mind to...
Thanks for the reply guys..
But when i increase the area of the transistors, which are contributing more for noise, the other parameters are changing. For example Phase margin is changing cosiderably(less than 0•).
Can u suggest any other efficient method...
auto zeroing to reduce flicker noise
I have designed a fully differential op amp in gain-boosting topology with 0.18µm technology, and i used ELDO simulator. I got input referred noise of 60nV/√Hz at 1KHz frequency, and 3nV/√Hz at higher frequencies.
So can any one suggest how to...
I have designed a Fully differential op amp with gain boosting topology in 0.18um technology in ELDO environment. It is designed in such a way that its I/P CM voltage is of 0.65V. If the input offset voltage is other than this, the operation of other transistors is changing from saturation...