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explanation of xor & x and gate
It's all right, spartan.
It's becoming interesting now, Even in real world we can not say for sure what will be the output.
<Unknown> XOR "1" = <Opposite of Unknown>
<Unknown> XOR "0" = <Unknown>
<Unknown> XOR <Unknown(which can be either 1 or...
xor gate german
Probably you haven't referred the verilog LRM. For your reference, I have attached a page from the LRM with this post.
Please, have a look at it. Your doubt will get clear after seeing the image.
I tried running your stuff as below, i don't see any problem.
Output is also shown below.
Please, post your testbench. May be something is wrong with the testbench.
module gen_chk(in1,in2, sig1,sig2);
input [4:0] in1;
input [3:0] in2;
output [4:0] sig1;
output [3:0] sig2 [4:0];
verilog generic parameters
First of all Verilog does not support more than one dimensional ports declaration.
You can use define, but you will have to specify it at compile time. You can not change it run time(h/w can not reduce/generate at run time :D).
If you want different number of...
insertion delay clock arrival timing
clock skew is difference of clock signal arrival time between two flops.
If you have two flops which works on the same clock frequency but due to position in the chip they are farther from each other, then there is a possibility is that u will see this problem.
Seems like i misinterpreted the problem... :cry:
"The input data is a fix pattern . 800 input clocks carry in 800 data continuously,and the other 200 clocks carry in no data. ".
I thought 200 ideal cycle can come at any time, at the start, in between or in the end.... But that is not the case...