# Recent content by bharat_in

1. ### what does bit blasted netlist mean??

I recently came to know about gate level netlist files which are also bit blasted... now does anyone know what is the difference between normal netlist and bit blasted netlist??
2. ### how to pass array in mailbox??

How can one pass array in mailbox in VERA or SV??
3. ### Output of XOR gate whose both inputs are "X"

explanation of xor & x and gate It's all right, spartan. It's becoming interesting now, Even in real world we can not say for sure what will be the output. See, <Unknown> XOR "1" = <Opposite of Unknown> <Unknown> XOR "0" = <Unknown> So, <Unknown> XOR <Unknown(which can be either 1 or...
4. ### Output of XOR gate whose both inputs are "X"

xor gate german Probably you haven't referred the verilog LRM. For your reference, I have attached a page from the LRM with this post. Please, have a look at it. Your doubt will get clear after seeing the image.
5. ### Output of XOR gate whose both inputs are "X"

gating a digital output if all the inputs are X, then output would always be X, no matter which gate it is
6. ### i2c fsm designing doubts - what is debouncing circuit in I2C

Re: I2c doubts @heartfree Can you explain more about de-bouncing circuit usage in I2C ???
7. ### What is the difference between SAIF and EVCD file??

what is evcd Also how is the SAIF file used in power estimation??
8. ### st micro Interview Questions for circuit design

transistors interview questions Found some questions @http://www.angelfire.com/in/rajesh52/quest.html
9. ### Verilog Package File - compiler is throwing error

Re: Verilog Package File Also put (acute) before the name of define, when you use it. e.g. Caseaddr[7:0] Reg1 : reg <= '1'; Reg2 : reg <= '0'; - - Regn : reg <= '1'
10. ### Generate statement usage verilog

Hey, I tried running your stuff as below, i don't see any problem. Output is also shown below. Please, post your testbench. May be something is wrong with the testbench. module gen_chk(in1,in2, sig1,sig2); input [4:0] in1; input [3:0] in2; output [4:0] sig1; output [3:0] sig2 [4:0]; genvar...
11. ### Verilog Generic Input ports

verilog generic parameters First of all Verilog does not support more than one dimensional ports declaration. You can use define, but you will have to specify it at compile time. You can not change it run time(h/w can not reduce/generate at run time :D). If you want different number of...
12. ### insertion delay ,skew , latency

insertion delay clock arrival timing clock skew is difference of clock signal arrival time between two flops. If you have two flops which works on the same clock frequency but due to position in the chip they are farther from each other, then there is a possibility is that u will see this problem.
13. ### ignore lines from file while reading by fscanf in verilog

Is there any way to ignore commented lines in file, while reading data by using fscanf function in verilog?
14. ### Solution to interview question about coding

Re: interview question assign c= foo ? a:b; For above statement, what will be the value of c, when all foo, a and b are "z"?
15. ### An interview question? Is my answer right?

Seems like i misinterpreted the problem... :cry: "The input data is a fix pattern . 800 input clocks carry in 800 data continuously,and the other 200 clocks carry in no data. ". I thought 200 ideal cycle can come at any time, at the start, in between or in the end.... But that is not the case...