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Recent content by bgpradeep

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    How to set NoTimingCheck on a single instance in NC-Verilog

    Thanks for the reply..this method will work but i wanted to find a different way so that i don't have to modify the SDFfile everytime a new one is created...
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    How to set NoTimingCheck on a single instance in NC-Verilog

    Hi, I would like to know how i can set No Timing check on a specific instance and to ignore only the recovery time check or only hold time check on this instance in NC-Verilog? Thanks..
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    Novas Warning Regarding use of Automatic tasks

    Hi All, I am using some automatic tasks (Ex: tk_trial) inside my verilog code and i see some Warnings from fsdb dump as below in the log file: *Novas* Warning: Filter out automatic task/function "tb.tb_module.tk_trial". How can i get rid of these Warnings without removing automatic in the...
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    Settling Time and Power Consumption measurement in DAC

    Hi, How exactly is the measurement of the settling time and power consumption is carried out for a current steering DAC. Settling time is the time it takes for the output to settle with in 10%. Thanks
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    INL & DNL measurement of 10-Bit DAC

    dac inl dnl measurement Thanks for the reply. I wanted to know whether my measurement of DNL is proper. This is how i am carrying out the measurement: 1 LSB = Iref/2^10 = 19.5uA/2^10 = 19.043nA For 0000000001, Iout/2^10 = 19.5uA/2^10 = 19.043nA Therefore, DNL = 19.043nA - 1LSB = 0LSB For...
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    INL & DNL measurement of 10-Bit DAC

    testing of 10bit dac Hi All, For checking the INL & DNL, under what consideration the simulation time is set. Like for checking INL & DNL, i am giving different codes from 00....0 to 11...1 every time. I did not get for how much time the simulation should be run. .TRAN 0NS 50NS -> my current...
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    INL & DNL measurement of 10-Bit DAC

    inl and dnl measurement Hi All, I had doubt in the measurement of INL & DNL. 1) Is 1LSB = Iref/2^N Here what should be the Iref value as LSB current source has 20uA and MSB current source delivers (20uA * 16). Here LSB = 4bits & MSB = 6bits. Also should N be different or it should be 10...
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    DAC Output for input from 0000..00 to 1111...1

    I inverted the MSB bit and found that my output is following the output but the value is around 1.5V (input was 1V). What might be the reason for this. Can this be because of MSB current sources not generating the exact value of current. I have attached the output got after changing the MSB...
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    DAC Output for input from 0000..00 to 1111...1

    Thanks for the replies. I have attached the output for a sine input fed through A/D to the D/A. I am not getting why there is an inversion at the start and at the mid point. Thanks Pradeep
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    DAC Output for input from 0000..00 to 1111...1

    Its actually a 10-Bit DAC Added after 59 seconds: Is it a problem with the input i am providing? or some logical mistake
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    DAC Output for input from 0000..00 to 1111...1

    Hi All, Can anyone help me on why the DAC output is behaving as shown in the attached file. I have also attached the zoomed part. The simulation was run for 200US and the Clock was 10MHz. Thanks
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    Help me correct a DAC output

    Hi, The simulation of the DAC yielded a output as shown in the attached file. Can anybody please help me on how the correct output is got. Thanks Pradeep
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    How to measure SFDR of DAC

    Hi, I would like to know how the SFDR is measured while simulating DAC after layout. Thanks
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    Use of Pattern Generator for DAC

    Is there a command to specify counter with clock into the netlist which can be run in Eldo.
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    Use of Pattern Generator for DAC

    dac pattern generator Hi, I wanted to use the pattern generator to generate a step input for a 10-bit DAC in Eldo. But could not understand how exactly it is done and also how to use the clock signal(200MHz) with this. Can anyone please help me on this. Thanks Pradeep
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