Recent content by beta0

1. How can I convert Verilog code (gatelvel) to Schematic?

converting verilog to schematic capture Hi, You can try debussy or verdi
2. What is DFM and where do we check it?

DFM DFM stands for design for manufaction.....
3. error when run the LDV simulator

You need to point it at the cadence tools library (e.g. $CDS_INST_DIR/tools/lib)as well as your own library directory(e.g. EXPORT LD_LIBRARY_PATH=$ LD_LIBRARY_PATH:/home/xxx/xx/, the directory is your local directory which contain file libudm.so)
4. how to convert *.ape files to mp3

open ape files try foobar2000
5. Explanation of the WLM settings

what is wlm WLM here stands for wireload model. for top, it means all net use the same wireload as which used on the top level, so the wireload used on hierarchical cells has no effect. if you used the flattend design to layout, you can chose this mode; for enclosed,it means the wire load...
6. Why we fix Hold after CTS?

Hold avoid to insert too many buffers
7. Can function be used in Verilog RTL?

Re: function used in RTL Right, Function are usually used for implementation some combination logic at RTL level
8. what's difference between USB2.0 and USB1.1 ?

usb2.0 usb1.1 different PHY is the bigest diffrence

10. How I can exicute eda tool on windows-xp from linux server

you can try VNC, very easy to use
11. PIC micro and stepper motor schematics

stepper motor schematics https://www.microchip.com/stellent/idcplg?IdcService=SS_GET_PAGE&nodeId=1515
12. what is "delay_mode_unit" for ncverilog?

ncsim assign # delay mode no, delay mode is used for cell delay
13. What are the isolation cells and what is their significance in DFT?

Isolation Cell Isolation cells is used to prevent physical damage to sections of the IC that interface to power switch-off modules in low power design.
14. ne verilog and vhdl code book

A Practical Guide for Designing, Synthesizing, and Simulating ASICs and FPGAs using VHDL or Verilog （ HDL Chip Design ） by Douglas J. Smith
15. What does R mean in ncverilog -R?

ncverilog -R -R: The -R option lets you simulate the same snapshot multiple times using different simulator command-line options.