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Dear all,
may i know the pros and cons of the two above layout techniques. and provide some example of these two techniques in a schematics. like when is it best to use interdigitization and common centriod
thank you so much and have a good day
best regards
Re: Multiple MOS layout
thank you so much for the help.
dipak.rf, can you pls suggest any good books or tutorials for beginners like me?
Thank you so much
Dear all,
does anyone know how to layout a substrate pnp bjt? the layers i have are metal1, poly, pisland, nisland, nselect, pselect, nwell, pwell. please advise
thank you so much
best regards
hey all,
i am confuse with the layout of multiple MOS. for example, i have a MOS with a size of 10 and assume i divided them evenly into 4 MOS with the size 2.5 each. may i know the correct way to connect the gates and drain/source?
should they connect in series or parallel as shown in the...
Dear all,
Ｉdesigned a temperature sensor using TSMC 0.18um technology. the supply voltage is 1.8V and the sensing range is from -40 to 125C. the output of the sensor is around 400mV to 600mV. which i intend to supply into the comparators. However the input value to the gates of the comparators...
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