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simulink pfd block
Hi,
I try to model a PFD in Simulink with classical architecture : Flipflop, NAND Gate, ... when i connect the NAND output to the flipflop clear input, and i try to run a simulation with my PLL, i have an error. Simulink will indicate i have a loop... if i add a time delay...
a question about PLL
Maybe i think, when a PLL is locked, the tension from filter to VCO is very stable. For example, with a fourth order filter, we have a variation near nV for ns.
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