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Recent content by behzadmsl

  1. B

    #error directive-codevision AVR V2.07.7

    hey im using codevision 2.04.4a,and trying to use #include<stdio.h> in my codevision project, but i got the error below : "Library error: C:\cvavr2.05.3\lib\stdio.lib(9): #error directive: Standard C I/O library must be used with CodeVisionAVR V2.04.7 or later" So I wrote my project using...
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    can't understand this ARM CMSIS code

    hi I'm trying to learn ARM nxp lpc1768,and i also attempting to use CMSIS library in my projects.So i downloaded lpc17xx CMSIS Driver Library Manual to read. I'm bit confused with code,and unfortunately i can't compile the code in order to make it clear for myself.. what does "1<<21" mean...
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    cant understand this verilog code

    also had done it,but didn't work
  4. B

    cant understand this verilog code

    i have 1 module named A and 2 files with .v extension,named B and C.The point that should be considered is that B and C do not have any module-like definition,they just hold parameter values //----------------------------- `include "B.v" `include "C.v" module A (...); endmodule...
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    cant understand this verilog code

    rberek you were right,i have dozens of instantiations of pipereg in my code,which have different width of output ...thank you and also coffee worked
  6. B

    cant understand this verilog code

    thank you,u r clarification was useful,would "pipereg #(x,y) pip3(...);" act the same way? will it make delay on x and y ?
  7. B

    cant understand this verilog code

    what is the difference between these two expressions :"pipereg #(1) pip1(...);" and "pipereg #1 pip2(...);" Do both of them mean to have pip1 and pip2 after first cycle?!! or they are completely different??? module pipereg(....); . . . pipereg #(1) pip1(....)...
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    cant understand this verilog code

    As you know you can make transistor level design in verilog, here is the question,is it possible to implement this design on an FPGA ??
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    cant understand this verilog code

    if we reckon de3 as a sub-module for module de2,and we make an instantiation of de3 in de2 module,then how we can initialize de3 !?? e.g we should have our instantiation like this de3 de3_1(.TEST_BENCH(TEST_BENCH)) or we should do something else?!!
  10. B

    cant understand this verilog code

    you mean if "TEST_BENCH" is valid then "inout [40:0] tm4_devbus;" port would be available and if it is not then we will have "wire [40:0] tm4_devbus;" and also a TEST_BENCH will be declared with these ports :"output JVC_CLK;","output JVC_CS;","output JVC_DATAOUT;"input JVC_DATAIN;" ???
  11. B

    cant understand this verilog code

    could u please clarify this module !! whats the meaning of having an `ifdef clause in module?? module de3 ( OSC1_50, `ifdef TEST_BENCH tm4_devbus, `endif `ifndef TEST_BENCH , JVC_CLK, JVC_CS, JVC_DATAOUT, JVC_DATAIN `endif...
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    cant understand this verilog code

    i got it,rhank u
  13. B

    cant understand this verilog code

    thank u,Couldn't it be defined this way ?? output mem_odt ; output mem_cs_n; output mem_cke;
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    cant understand this verilog code

    hi,what does this code mean?? Why it's been defined this way?? output [0:0] mem_odt; output [0:0] mem_cs_n; output [0:0] mem_cke;
  15. B

    help with verilog code

    i have written parts of my code ,processor is my top level module,and another thing to add is that "mem_dcache_wb" module has "altsyncram" megafunction which its input 'a' has been assigned with "bus_writedata"... i wanna know why an 512 bits wide port has been connected to a 128 bits wide port...
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