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Recent content by beginner_EDA

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    Division in xilinx ultrascale+ using DSP

    @ads-ee Hi, is it allowed to post on this forum the instantiation code of only DSP block I see under ultrascale+ device "DSP48E2" ? I have some question about setting some parameters of it. Furthermore If I do addition (A<=A+M) or subtraction(A<=A-M), how I know if synthesis tool/vivado...
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    Division in xilinx ultrascale+ using DSP

    IP -> complexity reason. LUT can be used. How to use LUTs for the division in pipelined format that passed timing? 1601477148 can you give me some hints how to write Verilog for division. I saw some radix 2 algorithm but its seems to be not easy.
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    Division in xilinx ultrascale+ using DSP

    I don't need it in a single clock and can be pipelined. However the requirement is not to use Xilinx IP(divider) but just DSP blocks. Can you point me to such design from Xilinx if you already know?
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    Division in xilinx ultrascale+ using DSP

    dividend and the divisor vary. I think this is the write one: https://www.xilinx.com/support/documentation/ip_documentation/div_gen/v5_1/pg151-div-gen.pdf
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    Division in xilinx ultrascale+ using DSP

    Hi, I have a design running at 125 MHz (8ns Pulse) and I do a large number division (125000000/115200) in system Verilog and it consumes 43 LUTs and 130 CARRY8 and have 34.087ns data path delay and that leading to -26.233ns setup timing violation. I would like to do it using dsp/ip core, if it...
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    System Verilog: ASCII 2 digits printout

    Hi, as per ASCII Table https://www.asciitable.com/ h30 to h39 is 0 to 9. I would like to print 0 to 32 but when I use this: generate for (genvar w=0; w<32; w=w+1) begin assign name[w] = {"name",8'h31+w}; end endgenerate its prints right from 0 to 9 but...
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    Clock Skew problem in oserdes

    Hi, I am using oserdes in Xilinx xcvu3p and run into following clock skew problem. (see attachment). I tried this http://www.xilinx.com/support/answers/67885.html but it didn't help. Any idea?
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    Set timing delay in lattice diamond for MACHXO2

    Hi, I would like to know how to set delay in lattice diamond for internal pins as well as for I/O? I put this inside .sdc file but it is not recognized what other tool like vivado recognize? set_max_delay -from [get_pins {I_module_a/txdata_reg[8]}] -to [get_pins {I_module_b/ODDRXE_msb}] 2.49...
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    [SOLVED] verilog set parameter to a module

    Hi, I came across following generated code from vivado: (* EXAMPLE_SIMULATION = "1" *) (* SIM_SPEEDUP = "FALSE" *) some_ip some_ip_inst( .a(a), .b(b) ); I know to set parameter inside module we use this way: some_ip #( .EXAMPLE_SIMULATION (1), .SIM_SPEEDUP...
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    Link Training with IO DELAY

    There is no specific protocol. I have just 4 I/O pins on TX end and 4 I/O pins on RX end and using 2 in one direction and remaining 2 on another direction at each end. At the moment I send some known pattern from each end and verify on another end and then send the data and it works at 100 MHz.
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    Link Training with IO DELAY

    @shaiko This solution seems like source synchronous. Is there one which is not source synchronous and also support smaller FPGA like artix?
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    Link Training with IO DELAY

    @shaiko, is this training also with IO DELAY? I see in page 315 https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_1/ug974-vivado-ultrascale-libraries.pdf IDELAYE3 primitive.
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    Link Training with IO DELAY

    Hi, how to implement link training with IO DELAY in Xilinx ultrascale FPGA? Any idea or reference design? Thanks
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    Verilog Assignment with condition

    always @(posedge clk) begin x<=1'b1; // First Assignment if (y) begin //some condition met x <= 1'b1; // Second Assignment end end I would like to know in above code when also condition met which assignment will be executed although both assignments are...
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    LPC data transfer Method

    Hi All, Is this feasible then ? Data -> 8b10b Encoder -> 10:1 serializer -> 1 pair LVDS(available 2 pins) -> 1:10 deserializer -> 8b10b Decoder -> Data
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