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Thanks for your replies, they are very helpful.
When I set in the GUI gnd layer: nxwell psub, I get the expected results in a simplified layout experiment! Also the extraction of the pwell connected to vdd (for the pmos varactor) looks fine. :) The issue with the NWELL seems to be solved :)...
I have a circuit with a large PMOS area consisting of current mirrors. Between the PMOS gate and VDD, there is a big capacitor, based on a pmos in pwell varactor (DNW underneath, pwell biased to vdd). Hence, the well of the PMOS and the capacitors are all biased to VDD.
When I run Calibre xRC...
I would advise you to use MonteCarlo proces+mismatch to determine the accuracy:
1) mismatch can cause additional errors
2) Standard corners do not offer much variation in the BJT's. Often the BJT corner (fast/slow) is correlated with the resistors.
3) min/max values with a given accuary (e.g...
1) You say that the effect you observe in case of a nonzero vsb corresponds with the theory. What does this theory say about what really happens?
2) Try to simulate with more accuracy and see whether the drop still occurs
3) The limits are set by the foundries, often max 50u in .13 or .18...
Ok, so your nmos is working in weak inversion (subthreshold), as your Vth will probably be around 400-500mV.
I guess that you want to compare your results with the formula Id=W/L I0' *exp[(vgs-vth)/nUT]. Vth is strongly dependent on the length and in case of very small widths also width...
What do you mean with: " The transistor is powered in the threshold regime at 250mV".?
The common terms to describe the operation region of a mosfet is either weak inversion (sometimes called sub-threshold) or strong inversion. The region between strong and weak inversion is called moderate...
I never used that specific option in ADEXL, but it should be easy to find it out yourself:
- what does the documentation say (click help in that particular menu).
- Test it out yourself with a simple circuit (e.g. only 1 diode connected transistor) and do seperate runs for mismatch and process.
It depends on the tools and PDK. Some PDK's have different transistors in the library for monte carlo simulations. In other PDK's it's an option in the transistor properties.
In AdeXL you can also select which devices should be included in the monte carlo analysis.
My reply wasn't really complete. Sorry. Maybe PSRR is also not that important yet.
Anyway, you can simulate the PSRR by setting a AC source in series with your supply voltage source. Then measure the bias voltage (either pmos or nmos, nmos will probably have a better value). You can see in this...
Yes, that is a good way to determine the temperature coefficients of the different resistors. You can now plot the resistor value by plotting 1/i(resistor) if you have a 1V supply.
You can also do it with a current source instead of voltage source, you then only have to plot the voltage at the...
The picture that Zeker posted is not a PTAT current source. You know that the difference of 2 PN junctions gives a PTAT voltage. This PTAT voltage makes a PTAT current using Rptat. The VBE voltage across the PNP is CTAT. By adjusting RpTAT, you can make the current through the currnet mirror...
From what I remember you could get an accuracy of ~2% over temperature when you compensate with a PTAT and CTAT current. Then you get indeed an inversed parabola.
Adding currents together isn't that hard: e.g. mirror the PTAT and CTAT current to a PMOS transistor. Then connect the drains of these 2 PMOS together. Connect that to a nmos mirror and you have the sum of 2 currents... :)
The challenge is to make sure that the PTAT and CTAT current have the...
It is important the transistors in a current mirror have the same size. So if the PMOS transistor in the beta multiplier is 10/0.5um, then you must also use these transistor sizes in the PMOS in your OTA that you are biasing with this current. If you want to increase the current (e.g. with a...
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