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in a CMOS circuit, what is meant by drive strength ? For example in TSMC cell library there are cells labeled AOI221X1 AOI221X2 etc. What is the significance of X1, X2 etc. Kindly give me a detailed reply by stating the defenition of drive strenth, signaifcance and factors affecting drive...
I am using fc4 and suddenly all desktop settings changed and all my control panel setting changed. Now I am unable to bring workspace switcher in to control panel. Kindly help me to solve this.
For given large combinational or sequentail gate level circuit, how can I calculate total switching transitions (0->1 and 1->0) provided that two input vectors in sequence.
Kindly suggest one efficient idea so that I can implement it effectively
I have installed beamer class as root and class fiel are stored in the directory
/usr/share/texmf/tex/latex/beamer/base. But while I am trying to run one simple tex program it is showing error as shown below.
ash-3.00$ latex test.tex
This is TeX, Version 3.14159 (Web2C 7.4.5)
Re: gate delay
In order to justify the concept, I calculated the AND gate delays (50%) for 130,90,65 and 45nm tech... in eldo. The result is given below , but this values are not correlating properly. Could you please cpmment on it ?
I have a basic doubt in gate delays. When we analyze the gate delay of and gate in 90nm , 65nm and 45nm technology which one is more. Pl. give me proper exlanation and justification for the same
spice gate delay
Ur explanation is lcear for me. But this delay and EDA tool delay calculaion need not be same. Anyway I will try with spice. BTW do you have any idea abt the interconnect delay analysis using spice. There r transmission line model in spice but will it be suitable for...
Sorry for the confusion. I will explain my problem in a detailed manner. We have magma tool eith 130nm TSMC libarry. But i have to calculate the delay of one deoder circuit for 90nm technology. If I kbnow the gate then I can calculate the Total delay of the circuit. So is there any...