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I am not using a specific tool to create the .lib file..
I am using cadence ADE to simulate the analog block. The simulation is controlled by an ocean script to iterate through all corners and list items to be specified in my timing arcs and. The results are then formatted for the lookup tables...
It looks to me that the simulator is having trouble finding a solution due to convergence problems. The reason for this can be many fold.. You can try standard convergence solving routines
- http://www.intusoft.com/articles/converg.pdf
- consult google
good luck!
Your question is a bit unspecific since it strongly depends on the available die size, technology and metal stack. There is no typical IC since all of them are very purpose specific. You should also ask yourself how many pins you will need since that is also important factor in how small the die...
Hello
I am currently composing a liberty timing file for an analog block to be used in a larger digital simulation. The pin description for most pins are only described by their direction, capacitance and rise_ -and fall_capacitance. What I can't figure out is how these latter values are...
According to Andrew Beckett in the Cadence Forums my original approach is not possible. Therefore I have changed my approach a bit. I added the delay parameter i neet to change to the cell using pPar("delay"). In that way the netlister adds the parameter directly to the instance call instead of...
I am trying to manipulate the parameters of a single instance of an array (I1<1024:1>). The instances contain a simple RC network and a current source modelling a rather complex circuit. All the instances are connected in series using a bus-notation. Now I need to add a unique delay to every...
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