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Recent content by barkha

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    [SOLVED] Re: Multi cycle paths

    Re: Multi cycle paths Multi-cycle constraints provided by Designer only , if that path is intended to meet only in multi-cycle. You can always check with designer whether any MCP is missed there OR that is genuine path to meet only in single cycle.
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    XOR gate used in DFT compression logic

    Why only XOR gate used in DFT compression logic ?
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    VHDL code for Binary to BCD

    few useful links **broken link removed** VHDL coding tips and tricks: VHDL code for BCD to 7-segment display converter **broken link removed** **broken link removed** 16 bit alu using vhdl It would be good if you try design and code by yourself first and then see other's code
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    VHDL code for Binary to BCD

    Link : Conversions might be useful ---------- Post added at 19:24 ---------- Previous post was at 19:23 ---------- Conversions see this link
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    Number of flops in Synchroniser flops !

    Useful Link : What Is Metastability?
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    APB read - do I need to consider penable

    As per APB protocol , In the case of a read, the slave must provide the data during the ENABLE cycle. The data is sampled on the rising edge of clock at the end of the ENABLE cycle. AMBA specification link - **broken link removed**
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    Design Compiler Verilog output - in a single module

    You have generated hierarchical netlist, you can flatten the netlist as mentioned.
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    Suggest me some books/websites on Digital Electronics

    Re: Digital Electronics Good Link - https://asicdigitaldesign.wordpress.com/
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    Address scarmbling?????

    Scrambling means that the logical structure, as seen by the user from the outside of the chip, differs from the physical or topological internal structure of the chip. The consequence is that logically adjacent addresses may not be physically adjacent (this is called address scrambling) and that...
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    Help me write a test bench for full adder and 4:1 mux?

    Re: test bench Refer book to understand design and test bench writing : Hdl Chip Design: A Practical Guide for Designing, Synthesizing & Simulating Asics & Fpgas Using Vhdl or Verilog by Douglas J. Smith Also below link is useful http://www.ece.umn.edu/class/ee4301/ExamplePage.html
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    Asic design and verification interview questions

    fpga design interview questions Hi, This Pdf contains lots of interview questions , might be useful : Link http://in.geocities.com/avvaru_theja/Interview_vlsi.pdf
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    What simulator are used for Verilog programming?

    Re: Verilog Help Modelsim,VCS any simulator you can use
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    Multi port memory controller for project work

    Hi, I need help to decide the academic project. I am thinking about the "Multi port memory controller". What are the interface I should support (AHB,AXI etc.) and which memory I should take for the controller design. I need to complete this project within 2-3 months. Please give some...
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    Bad habit in Verilog HDL

    Link is good - csg.csail.mit.edu/6.375/papers/cummings-nonblocking-snug99.pdf eesun.free.fr/DOC/VERILOG/synvlg.html
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    Where to start learning HDL advanced design?

    Re: HDL advanced design Hdl Chip Design: A Practical Guide for Designing, Synthesizing & Simulating Asics & Fpgas Using Vhdl or Verilog by Douglas J. Smith This book is very good to understand the concepts... Link:

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