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Recent content by bangash

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    Help needed : NS2 Problem

    ns2 trace packet type exp cbr Hi I am doing project on NS2. I have got stuck. I am generating two different type of traffic sources at a node(n0). Source 1 (CBR Traffic) has destination node(n1) and source 2 (Exp Traffic) has destination node(n2). I am monitoring queue at node n0 using...
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    Cool Mathematical Trick

    Math Problem? Its just shifting your first three nos and then adding the last 4 digits but still cool. Many people wont find it that easy
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    Ideas for projects about the recent networking trends

    Projects.... Try to implement WCDMA on FPGA. Its really a nice project
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    FPAA ( feild programmable analog arrays)

    This presentation will help
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    What are RF design engineers doing?

    Can anybody help me out with RF Design Engineer. 1. What is their job about?? 2. What are the fields they are expert in?? 3. What type of courses they study?? 4. What are its job prospects?? Waiting for reply
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    What are the applications of vitterbi decoder?

    vitterbi decoder check out www.complextoreal.com/tutorials You will find tutorial on convolutional encoder and viterbi decoder
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    What to use for circuit simulation: VHDL or Verilog?

    vhdl or verilog go for verilog first.its easy
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    what is the value of the function

    zero come on use some portion of your brain
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    What is the source encoding technique used in IS-95 system?

    IS-95 these three steps are performed in following order crc convolutional encoder block interleaver
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    How to do Viterbi decoding in Matlab

    Vetrbi Decoding ? its present in simulink model of matlab.
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    doubt in convolutional encoding

    constraint length is the no. of regs in your encoder.take this exp, constraint length of 9 corresponds to inputbit+8 regs. check tutorial on www.complextoreal.com
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    help me out with this warning

    xst:1336 more than 100% resources used. i have designed wcdma transceiver.now, in last step i get this warning.what should i do.it is referring to the multpliers. individual modules are using less than 100% resources but when combined into final module, the individual resources det summed up...
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    how to initalize master clock in xilinx spartan 3

    i want to set master clock to 122.88 mhz. how???
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    how to initalize master clock in xilinx spartan 3

    hi how i initalize system clock in xilinx. i mean what should i mention for it. clock,clk,Clock,Clk...... what???
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    Need Verilog code for Viterbi decoder

    hi, i need verilog code for viterbi decoder. data has been encoded with convolutional encoder of rate 1/3 and constraint span of 9. its urgent plz.........

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