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We used old spartan device which was 5V I/O tolerant. That device is obsolete one.Now, we are going to replace with new FPGA (SPARTAN3 series).But,these devices which are now in market are 3.3V tolerant only.How to face this problem?
Please suggest me.
I need a Processor BFM for our test environment to verify our AMBA AHB system.
Please I need suggesion. Can I get free BFM's for any processors to test our environment.
Basically, We need processor BFM which can work like a MASTER and to configure our ARBITER.
Any inputs are welcome!
I am looking for a BFM for simple,generic processor.I am very much new for writing BFM.Any inputs are welcome.Actually, whether BFM can be written systemverilog also.What is the preferred choice?We have our designs in systemverilog.I want to see the example codes for BFM for any module.
convert mealy machine to moore machine
This following explanation is for tronix...
As I previously said,u should have tried on ur own by solving a simple sequence detector.it's ok...
now we take a sequence detector which whas to detect bit sequence of 101... ok...
Let me say.....
already it has...
difference between moore and mealy
Please go through any text book covering both machines.
Whether it is mealy or moore,next state depends on both input a well as present state.
only the difference is Output where u will take. ...in mealy,output depends on present input as...
1)Indian Institute of science---ofcourse as it is a govt organisation,u need to follow certain interviews and show better performance.
2)MS ramaiah college.
3)Tejas Design centre also offers you a course which will enable you to get vlsi career.
Re: Universal Gates
I already mentioned all possible universal gates in this post.
XOR is not an universal gate.can u form NAND gate or NOR gate with using only XOR gate...?try...u can't.so XOR is not an universal gate.If u can form NAND gate(which is an universal gate) using XOR gate,then...
Re: Universal Gates-Mux,Inhibit,implication,HA etc.
Universal gates are those from which we can produce all kind of gates.
following are the examples.
6)XOR WITH AND
i want to learn CAD algorithms to enable layout of analog,rf,mixed signal,SOC'S.
I WANT TO LEARN CAD algorithm development for VLSI.
can anybody suggest any good books,web sites,course notes,etc....
i am doing layout in tanner Ledit.in a few days,we may get cadence licences.
so,is there any possibility of exporting tanner ledit to cadence layout.?
pls tell me urgently.
and i also want to know other free RF Layout tools.
thanks in advance.
i designed a circuit for LNA.i simulated for s parameters.i wanted to do pss analysis to find out 1 db compression point and iip3.i am getting problems by setting the analysis(specifying the parameters in the analysis window).can anybody help in this regard..or post any help material...
cadence noise figure simulation
we r having cadence licences and that too version 5.0.0.so we have spectre rf simulation facility.the problem is ...as we r in the institute, we r not able to see online documentation .
regarding ....finding out s parameters,we have to specify the ports.let...